STA333IS datasheet(34/43 Pages) STMICROELECTRONICS

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STA333IS

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DocID022855 Rev 4

5.7

Fault-detect recovery constant registers (addr 0x2B, 0x2C)

The FDRC bits specify the 16-bit fault-detect recovery time delay. When status register bit

FAULT is asserted, the tristate output is immediately asserted low and held low for the time

period specified by this constant. A value of 0x0001 in this register is approximately

0.083 ms. The default value of 0x000C gives approximately 0.1 ms.

Note:

0x0000 is a reserved value for this register pair. This value must not be used.

5.8

Device status register (addr 0x2D)

This read-only register provides the fault, warning and PLL status from the power control

block.

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

PLLUL

FAULT

UVFAULT

OVFAULT

OCFAULT

OCWARN

TFAULT

TWARN

Table 45. Status bits description

Bit

R/W

RST

Name

Description

0RO

TWARN

Thermal warning:

0: junction temperature is close to the fault condition

1: normal operation

1RO

TFAULT

Thermal fault:

0: junction temperature limit detection

1: normal operation

2RO

OCWARN

Overcurrent warning:

0: warning

1: normal operation

3RO

OCFAULT

Overcurrent fault:

0: fault detected

1: normal operation

---

Reserved

UVFAULT

Undervoltage warning:

0: VCCx below lower voltage threshold

1: normal operation

6RO

FAULT

Power bridge fault:

0: fault detected

1: normal operation

PLLUL

PLL lock:

0: locked

1: not locked

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