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DS160PR810 Datasheet(PDF) 30 Page - Texas Instruments |
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DS160PR810 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 39 page ![]() 10.2 Layout Example Place decoupling capacitors close to VCC and VREG1,2 pins; minimize ground loops Ensure pair-pair gap is > 5W* for minimal pair-pair coupling Top Layer Route high-speed traces as differential coupled microstrips (S=2W*) with tight impedance control (±10%) Use ac-coupling capacitors with 0201 package *W is a trace width. S is a gap between adjacent traces. Ensure high-speed trace length is matched with ” 5 mils intra-pair; pair-pair skew is less critical Avoid acute angles when routing high- speed traces Add ground pours for additional isolation Bottom Layer Follow connector manufacturer guidelines Use recommended package footprint and ground via placement Figure 10-1. DS160PR810 Layout Example - Sub-Section of a PCIe Riser Card With CEM Connectors DS160PR810 SNLS658 – DECEMBER 2020 www.ti.com 30 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DS160PR810 |
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