DS160PR810 datasheet(4/39 Pages) TI2

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Pin Functions

I/O, TYPE

DESCRIPTION

NAME

NO.

ALL_DONE_N

O, 3.3 V open

drain

In SMBus/I2C Master Mode:

Indicates the completion of a valid EEPROM register load operation. External pullup

resistor such as 4.7 kΩ required for operation.

High: External EEPROM load failed or incomplete

Low: External EEPROM load successful and complete

In SMBus/I2C slave/Pin Mode:

This output is High-Z. The pin can be left floating.

MODE

I, 4-level

Sets device control configuration modes. 4-level IO pin as defined in Table 7-1. The pin

can be exercised at device power up or in normal operation mode.

L0: Pin Mode – device control configuration is done solely by strap pins.

L1: SMBus/I2C Master Mode - device control configuration is read from external

EEPROM. When the device has finished reading from the EEPROM successfully, it will

drive the ALL_DONE_N pin LOW. SMBus/I2C slave operation is available in this mode

before, during or after EEPROM reading. Note during EEPROM reading if the external

SMBus/I2C master wants to access the device registers it must support arbitration.

L2: SMBus/I2C Slave Mode – device control configuration is done by an external

controller with SMBus/I2C master.

L3 (Float): RESERVED – TI internal test mode.

EQ0_0 / ADDR0

I, 4-level

In Pin Mode:

Sets receiver linear equalization (CTLE) for channels 0-3 according to Table 7-3.

These pins are sampled at device power-up only.

In SMBus/I2C Mode:

Sets SMBus / I2C slave address according to Table 7-4. These pins are sampled at

device power-up only.

EQ1_0 / ADDR1

I, 4-level

EQ0_1

I, 4-level

Sets receiver linear equalization (CTLE) for channels 4-7 according to Table 7-3 in Pin

mode. The pin is sampled at device power-up only.

EQ1_1

I, 4-level

Sets receiver linear equalization (CTLE) for channels 4-7 according to Table 7-3 in Pin

mode. The pin is sampled at device power-up only.

GAIN0 / SDA

I, 4-level / I/O,

3.3 V

LVCMOS,

open drain

In Pin Mode:

Flat gain (DC and AC) from the input to the output of the device for channels 0-3. The

pin is sampled at device power-up only.

In SMBus/I2C Mode:

3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /

I2C interface standard.

GAIN1

I, 4-level

Flat gain (DC and AC) from the input to the output of the device for channels 4-7 in Pin

mode. The pin is sampled at device power-up only.

GND

EP, 9, 12, 21,

24, 32, 41, 44,

53, 56, 64

Ground reference for the device.

EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return

for the device. The EP should be connected to ground plane(s) through low resistance

path. A via array provides a low impedance path to GND. The EP also improves

thermal dissipation.

PD0

I, 3.3 V

LVCMOS

2-level logic controlling the operating state of the redriver. Active in all device control

modes. The pin has internal 1-MΩ weak pulldown resistor.

High: Power down for channels 0-3

Low: Power up, normal operation for channels 0-3

PD1

I, 3.3 V

LVCMOS

2-level logic controlling the operating state of the redriver. Active in all device control

modes. The pin has internal 1-MΩ weak pulldown resistor.

High: Power down for channels 4-7

Low: Power up, normal operation for channels 4-7

READ_EN_N

I, 3.3 V

LVCMOS

In SMBus/I2C Master Mode:

After device power up, when the pin is low, it initiates the SMBus / I2C master mode

EEPROM read function. Once EEPROM read is complete (indicated by assertion of

ALL_DONE_N low), this pin can be held low for normal device operation. During the

EEPROM load process the device’s signal path is disabled.

In SMBus/I2C Slave and Pin Modes:

In these modes the pin is not used. The pin can be left floating. The pin has internal 1-

MΩ weak pulldown resistor.

RSVD0

—

Reserved use for TI. The pin must be left floating (NC).

DS160PR810

SNLS658 – DECEMBER 2020

www.ti.com

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