INA230 datasheet(21/44 Pages) TI2

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Frame 1 Two-Wire Target Address Byte

(1)

Frame 2 Register Pointer Byte

Start By

Controller

ACK By

Target

ACK By

Target

SDA

SCL

R/W

Stop

(1) The value of the Target Address byte is determined by the setting of the address pins. Refer to Table 7-2.

Figure 7-7. Typical Register Pointer Set

7.5.6.1 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup devices. The controller generates

a start condition followed by a valid serial byte containing High-Speed (HS) controller code 00001XXX. This

transmission is made in fast (400kHz) or standard (100kHz) (F/S) mode at no more than 400kHz. The INA230

does not acknowledge the HS controller code, but does recognize the code and switches the internal filters to

support 3.4MHz operation.

The controller then generates a repeated start condition (a repeated start condition has the same timing as

the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 3.4MHz are allowed. Instead of using a stop condition, repeated start conditions must

be used to secure the bus in HS-mode. A stop condition ends the HS mode and switches all the internal filters of

the INA230 to support the F/S mode.

7.5.7 SMBus Alert Response

The INA230 is designed to respond to the SMBus alert response address. The SMBus alert response provides

a quick fault identification for simple target devices. When an alert occurs, the controller can broadcast the

alert response target address (0001 100) with the Read/Write bit set high. Following this alert response, any

target devices that generated an alert identify themselves by acknowledging the alert response and sending the

respective address on the bus.

The alert response can activate several different target devices simultaneously, similar to the I2C general call. If

more than one target attempts to respond, bus arbitration rules apply. The losing device does not generate an

acknowledge and continues to hold the ALERT line low until the interrupt is cleared.

7.6 Register Maps

The INA230 uses a bank of registers for holding configuration settings, measurement results, minimum and

maximum limits, and status information. Table 7-3 summarizes the INA230 registers; refer to the Functional

Block Diagram for an illustration of the registers.

All 16-bit INA230 registers are two 8-bit bytes through the I2C interface.

Table 7-3. Summary of Register Set

POINTER

ADDRESS

FUNCTION

POWER-ON RESET

TYPE(1)

HEX

BINARY

HEX

Configuration

All-register reset, shunt voltage and

bus voltage ADC conversion times and

averaging, operating mode

01000001 00100111

4127

R/ W

Shunt Voltage

Shunt voltage measurement data

00000000 00000000

0000

Bus Voltage

Bus voltage measurement data

00000000 00000000

0000

Power(2)

Contains the value of the calculated

power being delivered to the load.

00000000 00000000

0000

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INA230

SBOS601B – FEBRUARY 2012 – REVISED JANUARY 2025

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