VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CLOCK OUTPUT FOR VDD = 1.8 V ± 5%

VOH

Output high voltage

IOH = 1 mA

0.8 x VDD

V

VOL

Output low voltage

IOL = 1 mA

0.2 x VDD

tRISE-FALL

Output rise and fall time

20/80%, CL= 5 pF, fIN = 156.25 MHz

0.38

1

ns

tOUTPUT-

SKEW

Output-output skew

See (4)

50

ps

tPART-SKEW Part-to-part skew

900

ps

tPROP-DELAY Propagation delay

See (5)

1.5

3

ns

tJITTER-ADD Additive Jitter

fIN = 156.25 MHz, Input slew rate = 2 V/ns,

Integration range = 12 kHz - 20 MHz

17.5

50 fs, RMS

ROUT

Output impedance

60

Ω

GENERAL PURPOSE INPUT (1G)

VIH

High-level input voltage

0.75 x

VDD

V

VIL

Low-level input voltage

0.25 x

VDD

IIH

Input high-level current

VIH = VDD_REF

–50

50

µA

IIL

Input low-level current

VIL = GND

–50

50

(1)

Measured from VDD stable to output active, when 1G = HIGH.

(2)

Measured from 1G rising edge crossing VIH to first rising edge of Yn.

(3)

Measured from 1G falling edge crossing VIL to last falling edge of Yn.

(4)

Measured from rising edge of any Yn output to any other Ym output.

(5)

Measured from rising edge of CLKIN to any Yn output.

7.6 Timing Requirements

VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C

MIN

NOM

MAX

UNIT

POWER SUPPLY

V/tRAMP

VDD ramp rate

0.1

50

V/ms

7.7 Typical Characteristics

Frequency (MHz)

0

25

50

75

100

125

150

175

200

225

250

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

D001

VDD = 1.8 V

VDD = 2.5 V

VDD = 3.3 V

Figure 7-1. Device Power Consumption vs. Clock Frequency (Load 5 pF)

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LMK1C1102, LMK1C1103, LMK1C1104

SNAS791D – DECEMBER 2019 – REVISED FEBRUARY 2022

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