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LP38690, LP38692

SNVS322M – DECEMBER 2004 – REVISED DECEMBER 2015

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Copyright © 2004–2015, Texas Instruments Incorporated

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Reverse Voltage

A reverse voltage condition exists when the voltage at the output pin is higher than the voltage at the input pin.

Typically this happens when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that

the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is

connected to the output.

There are two possible paths for current to flow from the output pin back to the input during a reverse voltage

condition.

1. While VIN is high enough to keep the control circuitry alive, and the EN pin (LP38692 only) is above the

VEN(ON) threshold, the control circuitry attempts to regulate the output voltage. If the input voltage is less than

the programmed output voltage, the control circuit drives the gate of the pass element to the full ON

condition. In this condition, reverse current flows from the output pin to the input pin, limited only by the

RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to

1000

μF in this manner does not damage the device as the current will rapidly decay. However, continuous

reverse current should be avoided. When the EN pin is low this condition is prevented.

2. The internal PFET pass element has an inherent parasitic diode. During normal operation, the input voltage

is higher than the output voltage and the parasitic diode is reverse biased. However, when VIN is below the

value where the control circuitry is alive, or the EN pin is low (LP38692 only), and the output voltage is more

than 500 mV (typical) above the input voltage the parasitic diode becomes forward biased and current flows

from the output pin to the input pin through the diode. The current in the parasitic diode should be limited to

less than 1 A continuous and 5 A peak.

If used in a dual-supply system where the regulator output load is returned to a negative supply, the output

pin must be diode clamped to ground to limit the negative voltage transition. A Schottky diode is

recommended for this protective clamp.