PCM5100APWR datasheet(33/44 Pages) TI2

33 / 44 page

PCM5100A, PCM5101A, PCM5102A

PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1

www.ti.com

SLAS859C – MAY 2012 – REVISED MAY 2015

11.5 PCM510xA Power Modes

11.5.1 Setting Digital Power Supplies and I/O Voltage Rails

The internal digital core of the PCM510xA devices run from a 1.8-V supply. This can be generated by the internal

LDO, or by an external 1.8-V supply.

DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V

required by the digital core.

For systems that require 3.3 V I/O support, but lower power consumption, DVDD should be connected to 3.3 V

and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO.

When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.

11.5.2 Power Save Modes

The PCM510xA devices offer two power-save modes: standby and power-down.

When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA device automatically enters

standby mode. The DAC and line driver are also powered down.

When BCK and LRCK remain at a low level for more than 1 second, the PCM510xA device automatically enters

powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition

to those disabled in standby mode.

When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start

correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup

sequence automatically.

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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100APWR Datasheet(PDF) 33 Page - Texas Instruments