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TCA9554 Datasheet(PDF) 8 Page - Texas Instruments |
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TCA9554 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 48 page  8 TCA9554 SCPS233E – MARCH 2012 – REVISED FEBRUARY 2017 www.ti.com Product Folder Links: TCA9554 Submit Documentation Feedback Copyright © 2012–2017, Texas Instruments Incorporated 6.6 I 2C Interface Timing Requirements over operating free-air temperature range (unless otherwise noted) (see Figure 11) MIN MAX UNIT STANDARD MODE fscl I2C clock frequency 0 100 kHz tsch I2C clock high time 4 µs tscl I2C clock low time 4.7 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1000 ns ticf I2C input fall time 300 ns tocf I2C output fall time 10-pF to 400-pF bus 300 ns tbuf I2C bus free time between Stop and Start 4.7 µs tsts I2C Start or repeated Start condition setup 4.7 µs tsth I2C Start or repeated Start condition hold 4 µs tsps I2C Stop condition setup 4 µs tvd(data) Valid data time SCL low to SDA output valid 3.45 µs tvd(ack) Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.45 µs Cb I2C bus capacitive load 400 pF FAST MODE fscl I2C clock frequency 0 400 kHz tsch I2C clock high time 0.6 µs tscl I2C clock low time 1.3 µs tsp I2C spike time 50 ns tsds I2C serial-data setup time 100 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 20 300 ns ticf I2C input fall time 20 × (VDD / 5.5 V) 300 ns tocf I2C output fall time 10-pF to 400-pF bus 20 × (VDD / 5.5 V) 300 ns tbuf I2C bus free time between Stop and Start 1.3 µs tsts I2C Start or repeated Start condition setup 0.6 µs tsth I2C Start or repeated Start condition hold 0.6 µs tsps I2C Stop condition setup 0.6 µs tvd(data) Valid data time 0.9 µs tvd(ack) Valid data time of ACK condition 0.9 µs Cb I2C bus capacitive load 400 pF 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 12 and Figure 13) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX UNIT STANDARD MODE and FAST MODE tiv Interrupt valid time P port INT 4 µs tir Interrupt reset delay time SCL INT 4 µs tpv Output data valid SCL P7–P0 350 ns tps Input data setup time P port SCL 100 ns tph Input data hold time P port SCL 1 µs |
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