MP3924GU datasheet(36/56 Pages) MPS

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MP3924

– QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER

MP3924 Rev. 1.0

MonolithicPower.com

7/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

2-EVENT_AND_CLASS_5_ENABLE (0Ch)

Read/write

Bits

Bit Name

Default Value

Description

D[7]

CLS5_EN4

Enables Class 5 classification for all ports. If these bits are set to 1, Class 5

classification is enabled on the corresponding port, and the default current limit

can support up to 40W of power.

D[6]

CLS5_EN3

D[5]

CLS5_EN2

D[4]

CLS5_EN1

D[3]

2EVNTEN4

Enables two-event classification for all ports. If these bits are set to 1, two-event

classification is enabled when the first classification result on the port is Class 4 or

Class 5.

D[2]

2EVNTEN3

D[1]

2EVNTEN2

D[0]

2EVNTEN1

“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low. “C” is

“1” if the CLS5 pin is set high during start-up or a reset. “C” is “0” if the CLS5 pin is set low. The CLS5

pin has a high power level under the IEEE802.3 at classification, but it is not a standard class level that

is compatible with IEEE802.3.

PMAX_SHUTDOWN_PORT_PRIORITY (0Dh)

Read/write

Bits

Bit Name

Default Value

Description

D[7:6]

PRTY4

Sets the shutdown priority for all ports after the PMAX limit is triggered. If the value

is the same on several ports, priority is arranged based on the default priority. For

example, if both port 1 and port 2 are 00, then port 2 shuts down first.

11: The lowest priority port, which shuts down first if the PMAX limit is triggered

10: The third level priority port if the PMAX limit is triggered

01: The second level priority port if the PMAX limit is triggered

00: The highest priority port, which shuts down last if the PMAX limit is triggered

D[5:4]

PRTY3

D[3:2]

PRTY2

D[1:0]

PRTY1

INTERRUPT_ENABLE_CONTROL (0Eh)

Read/write

Bits

Bit Name

Default Value

Description

D[7:3]

RESERVED

Reserved.

D[2]

CLRPIN

Controls the reset function for the INT1 and INT2 pins. If this bit is set to 1,

resetting the INT1 and INT2 pins does not affect the registers. This bit is

automatically set to 0 after the INT1 and INT2 pins are reset.

D[1]

CLRAINT

Controls the reset function for the interrupt source. If this bit is set to 1, all

registers and the INT1 and INT2 bit are reset. This bit is automatically set to 0

after the INT1 and INT2 pins are reset.

D[0]

INTEN

Enables the interrupt function. This bit does not affect the event register. If this bit

is set to 1, the interrupt function is enabled.

GENERAL_ENABLE_CONTROL (0Fh)

Read/write

Bits

Bit Name

Default Value

Description

D[7:3]

RESERVED

Reserved.

D[2]

PMAXEN

Enables the maximum total load power limit. If this bit = 1, automatic shutdown is

triggered when the PMAX pin reaches its maximum input power setting.

D[1]

ADCEN

Enables the ADC. If this bit = 1, the ADC is enabled.

D[0]

WDEN

Enables the I2C watchdog. If this bit is set to 0, the watchdog is disabled.

“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low.

MP3924GU Datasheet(PDF) 36 Page - Monolithic Power Systems

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