AD4081BBCZ datasheet(18/95 Pages) AD

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Data Sheet

AD4081

THEORY OF OPERATION

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Rev. 0 | 18 of 95

PRODUCT OVERVIEW

The AD4081 is a high speed, low noise, low distortion, 20-bit,

Easy Drive, SAR ADC. The device is capable of conversion rates

up to 20MSPS, with 77.50ns result output latency. The parametric

performance, bandwidth, and throughput make this product ideal for

a variety of high speed, data acquisition applications. Innovations in

the AD4081 product design enable both complexity reduction and

component flexibility in the design of data acquisition signal chains.

The converter architecture enables continuous acquisition of the in-

put signal throughout the entire conversion period, tCONV, reducing

the input signal conditioning bandwidth required to settle to the

specified resolution.

The design incorporates circuitry to reduce the nonlinear input

current associated with the charge kickback typical of a switched

capacitor SAR input.

Conversion result access occurs via either a multilane LVDS port

operating at clock rates up to 200MHz or via a multioutput SPI

operating at clock rates up to 50MHz.

The LVDS interface is compatible with differential signaling stand-

ards between 1.2V and 2.5V. To maximize throughput, the previous

conversion results can be read through the entirety of the conver-

sion period as long as the CNV+ edge and CLK+ rising edges are

aligned. The LVDS interface is described in detail in the LVDS Data

Interface Configuration section.

The single or quad lane SPI data interface is also available for

CMOS level interfacing. When configured, this interface is used

to access conversion results stored in the on-chip FIFO. FIFO

operation is explained in the Result FIFO section.

CONVERTER OPERATION

A conventional SAR ADC typically operates in two phases—an

acquisition phase, whereby the analog input voltage is acquired

on the analog input pins, and followed by a conversion phase

that is initiated by a conversion start signal. During the conversion

phase the sampled analog input voltage is converted to a digital

conversion result. In a single ADC, this is typically performed by

converting the voltage from one sampling circuit. In the case of

the AD4081, Figure 32 details the unique feature of this converter,

whereby the analog input is connected to two sampling circuits,

and the input is sampled by each one in sequence. To a user,

this requires no additional control or configuration, and as such, is

completely transparent in usage.

Figure 32. Simplified Representation of the AD4081 SAR ADC

The AD4081 converter seamlessly sequences back and forth from

one sampler to the other, meaning that one sampler is in acquisition

mode while the voltage sampled on the other is being converted.

Figure 33 shows that the AD4081 timing is contrasted against

a conventional SAR ADC, where it switches between sequential

conversion and the acquisition phase leads to a reduced amount

of time for the input signal acquisition and settling. As sampling

rates increase (and therefore cycle times reduce), it is important

to maintain longer acquisition times to enable settling, particularly

to the higher levels of precision offered by the AD4081. Further

details on the benefits of reducing driver and noise bandwidths are

described in the Easy Drive Analog Inputs section.

Figure 33. Conversion Cycle Compared to Conventional SAR

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