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TMP1075DR Datasheet(PDF) 8 Page - Texas Instruments |
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TMP1075DR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 49 page ![]() 6.7 Timing Requirements:TMP1075 minimum and maximum specifications are over –55°C to 125°C and V+ = 1.7 V to 5.5 V (unless otherwise noted)(1) FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX f(SCL) SCL operating frequency 0.001 0.4 0.001 2.56 MHz t(BUF) Bus-free time between STOP and START conditions 1300 160 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) Repeated START condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time(2) 0 0 130 ns t(SUDAT) Data setup time 100 20 ns t(LOW) SCL clock low period 1300 250 ns t(HIGH) SCL clock high period 600 60 ns t(VDAT) Data valid time (data response time)(3) 900 130 ns tFDA Data fall time 300 100 ns tR Clock rise time 300 40 ns tF Clock fall time 300 40 ns ttimeout Timeout (SCL = SDA = GND) 20 30 20 30 ms tRC Clock/ data rise time for SCL = 100 kHz 1000 ns (1) The host and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release. (2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time. (3) t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse). TMP1075 SBOS854F – MARCH 2018 – REVISED JUNE 2024 www.ti.com 8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TMP1075 |
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