LD7523GS datasheet(14/18 Pages) LEADTREND

14 / 18 page

LD7523

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7523-DS-00

June 2009

VCC

UVLO(on)

UVLO(off)

COMP

Over Load

OUT

OLP Delay Time

Switching

Non-Switching

OLP skip duration

OLP Delay Time

OLP skip duration

Over Load

Switching

OLP Delatch by

Internal Counter

Fig. 26

Over Voltage Protection (OVP)

To prevent the component from damage due to fault

condition, LD7523 is implemented with protection through

the OVP pin.

Figure 27 and figure 28 show 2 different

configurations to program the OVP setting point --- zener

detection and voltage divider.

It provides zero bias

current during normal operation so that it will not affect the

startup timing, as figure 27.

But the tolerance of OVP trip

point will be larger due to the distribution of the breakdown

voltage of zener diode.

On the other hand, using the circuit of figure 28 will be

beneficial from the minimum cost and higher OVP

accuracy, but it requires larger value of R1 and R2 to

avoid affecting on startup timing by the load effect.

As shown in figure 29, if the voltage on the OVP pin rise

above threshold voltage of 2.5V, the output gate drive

circuit will be shutdown simultaneous in order to stop

switching the power MOSFET.

But if the voltage on the

OVP pin drops below 2.5V, it will automatically resume to

the normal operation on the next UVLO(on) level.

VCC

GND

LD7523

OVP

Vbulk-cap

V(OVP)= Vz+2.5V

Fig. 27

)

(

)

(

OVP

⋅

Fig. 28

VCC

UVLO(on)

UVLO(off)

OVP Tripped

OUT

Switching

Non-Switching

OVP Level

Fig. 29

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