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TPS37100 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS37100 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 33 page ![]() Table 5-1. Pin Functions (continued) PIN TPS37100-Q1 TPS37102-Q1 I/O DESCRIPTION NAME NO. NO. BIST_EN - 11 I Built-in Self-test Enable: A rising edge input must occur on the BIST_EN to initate BIST. For variants with latch enabled in the configuration as denoted by in Section 4, BIST_EN enables or disables a latch on OUT A. See Section 7.3.7 for more details. CTR 12 12 - Release Time Delay: User-programmable release time delay for CTR enabled outputs OUT A and OUT B. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 7.3.4 for more details. CTS 13 13 - Sense Time Delay: User-programmable sense time delay for CTS enabled outputs OUT A and OUT B. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay when CTS is enabled. See Section 7.3.5 for more details. NC 2, 4, 6, 8, 14 2, 4, 6, 14 - NC stands for “No Connect.” The pins are to be left floating. TPS37100-Q1, TPS37102-Q1 SNVSCN2A – SEPTEMBER 2024 – REVISED SEPTEMBER 2025 www.ti.com 6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TPS37100-Q1 TPS37102-Q1 |
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