LTC7897 datasheet(42/53 Pages) AD

42 / 53 page

Data Sheet

LTC7897

analog.com

Rev. A

42 of 53

9. Select the input and output capacitors. CIN is chosen for an RMS current rating of at least 2A (IOUT/2, with

margin) at temperature. COUT is chosen with an ESR of 10mΩ for low output ripple. Multiple capacitors

connected in parallel may be required to reduce the ESR to this level. The output ripple in continuous

mode is highest at the maximum input voltage. The output voltage ripple due to ESR is approximately

given by Equation 35, as follows:

VORIPPLE = ESR • ∆IL = 10mΩ*1.4A = 14mVP-P

(35)

On the 12V output, 14mVP-P is equal to 0.12% of peak-to-peak voltage ripple.

10. Determine the bias supply components. Because the regulated output is greater than the EXTVCC

switchover threshold, it can be used to bias EXTVCC. For an 8ms soft-start, select a 0.1µF capacitor for the

TRACK/SS pin. As a first pass estimate for the bias components, select the DRVCC capacitance CDRVCC = 4.7µF,

CINTVCC = 0.1µF and CB = 0.1µF.

11. Determine and set application-specific parameters. Set the MODE pin based on the trade-off of light load

efficiency and constant frequency operation. Set the PLLIN/SPREAD pin based on whether a fixed, spread

spectrum, or phase-locked frequency is desired. The RUN pin can be used to control the minimum input

voltage for regulator operation, or it can be tied to VIN for always-on operation. Use ITH compensation

components from the typical applications as a first guess, check the transient response for stability, and

modify as necessary.

PC Board Layout Checklist

Figure 49 shows the current waveforms present in the various branches of the synchronous regulators operating in

the continuous mode.

When laying out the PCB, use the following checklist to ensure proper operation of the IC.

1. Route the BGUP and BGDN traces together and connect them as close as possible to the bottom MOSFET

gate. If using gate resistors, connect the resistor connections to the MOSFET gate as close as possible to

the MOSFET. Connecting BGUP and BGDN further away from the bottom MOSFET gate can cause

inaccuracies in the dead time control circuit of the LTC7897. Route the TGUP and TGDN traces together

and connect them as close as possible to the top MOSFET gate.

2. The combined IC GND pin and the GND return of CDRVCC must return to the combined COUT negative

terminals. The path formed by the top N-channel MOSFET and the CIN capacitor must have short leads and

PCB trace lengths. Connect the output capacitor’s negative terminals as close as possible to the negative

terminals of the input capacitor by placing the capacitors next to each other and away from the loop.

3. Connect the LTC7897 VFB pin resistive dividers to the positive terminals of COUT and the signal GND. Place

the divider close to the VFB pin to minimize noise coupling into the sensitive VFB node. The feedback resistor

connections must not be along the high current input feeds from the input capacitors.

4. Route the SENSE− and SENSE+ leads together with minimum PCB trace spacing. Route these traces away

from the high frequency switching nodes on an inner layer, if possible. The filter capacitor between SENSE+

and SENSE− must be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections

at the sense resistor.

5. Connect the DRVCC decoupling capacitor close to the IC, between the DRVCC and the power GND pin. This

capacitor carries the current peaks of the MOSFET drivers. Place an additional 1μF ceramic capacitor next

to the DRVCC and GND pins to help improve noise performance.

LTC7897 Datasheet(PDF) 42 Page - Analog Devices

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