TPS73601DBVR datasheet(18/48 Pages) TI2

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The TPS73601 adjustable version does not have the NR pin available. However, connecting a feedback

capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improves load transient

performance.

The TPS736 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of

the NMOS pass transistor above VOUT. The charge pump generates approximately 250μV of switching noise

at approximately 4MHz; however, charge-pump noise contribution is negligible at the output of the regulator for

most values of IOUT and COUT.

6.3.2 Internal Current Limit

The TPS736 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps

to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT

drops below 0.5V. See Figure 5-17 in the Typical Characteristics section.

Note from Figure 5-17 that approximately –0.2V of VOUT results in a current limit of 0mA. Therefore, if OUT

is forced below –0.2V before EN goes high, the device can not start up. In applications that work with both a

positive and negative voltage supply, the TPS736 must be enabled first.

6.3.3 Enable Pin and Shutdown

The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5V (max)

turns the regulator off and drops the GND pin current to approximately 10nA. When EN is used to shutdown the

regulator, all charge is removed from the pass transistor gate. A VEN above 1.7V (minimum) turns the regulator

on and the output ramps back up to a regulated VOUT (see Figure 5-40).

When shutdown capability is not required, connect EN to VIN. However, the pass transistor cannot be discharged

using this configuration, and the pass transistor can be left on (enhanced) for a significant time after VIN has

been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp

times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output can overshoot

upon power-up.

Current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section

for more information.

6.3.4 Reverse Current

The NMOS pass transistor of the TPS736 provides inherent protection against current flow from the output of

the regulator to the input when the gate of the pass transistor is pulled low. To ensure that all charge is removed

from the gate of the pass transistor, the EN pin must be driven low before the input voltage is removed. If this is

not done, the pass transistor can be left on due to stored charge on the gate.

After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Reverse current

is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There is additional

current flowing into the OUT pin due to the 80kΩ internal resistor divider to ground (see Figure 6-1 and Figure

6-2).

For the TPS73601, reverse current can flow when VFB is more than 1.0V above VIN.

6.4 Device Functional Modes

6.4.1 Normal Operation With 1.7V ≤ VIN ≤ 5.5V and VEN ≥ 1.7V

The TPS736 requires an input voltage of at least 1.7V to function properly and attempt to maintain regulation.

If the device output voltage is greater than 1.5V when the input voltage is at 1.7V, the device is operating

in dropout and regulation cannot be maintained. Because of the NMOS architecture used in the TPS736, the

dropout voltage is not a strong function of the input voltage.

When operating the device near 5.5V, take care to suppress any transient spikes that can exceed the 6.0V

absolute maximum voltage rating. The device must never operate at a dc voltage greater than 5.5V.

TPS736

SBVS038X – SEPTEMBER 2003 – REVISED MAY 2025

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