TPS53513 datasheet(16/44 Pages) TI2

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VREG

VDD

2.8 V

0.6 V

VREF/VDAC

VOUT

~ 400 µs

tSS (1 ms)

TPS53513

SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

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7.3 Feature Description

7.3.1 5-V LDO and VREG Start-Up

The TPS53513 device has an internal 5-V LDO feature using input from VDD and output to VREG. When the

VDD voltage rises above 2.8 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG

voltage provides the bias voltage for the internal analog circuitry. The VREG voltage also provides the supply

voltage for the gate drives.

Figure 33. Power-up Sequence Waveforms

7.3.2 Enable, Soft Start, and Mode Selection

The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin.

When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its start-

up sequence. The controller then uses the first 400 μs to calibrate the switching frequency setting resistance

attached to the RF pin and stores the switching frequency code in internal registers. During this period, the

MODE pin also senses the resistance attached to this pin to determine the operation mode. In the second phase,

an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. the ramping up time is 1 ms. The

device maintains smooth and constant ramp-up of the output voltage during start-up regardless of load current.

7.3.3 Frequency Selection

TPS53513 device lets users select the switching frequency by using the RF pin. Table 1 lists the divider ratio and

some example resistor values for the switching frequency selection. The 1% tolerance resistors with a typical

temperature coefficient of ±100 ppm/ºC are recommended. If the design requires a tighter noise margin for more

reliable SW-frequency detection, use higher performance resistors.

TPS53513 Datasheet(PDF) 16 Page - Texas Instruments