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DAC38RF82IAAV Datasheet(PDF) 39 Page - Texas Instruments

Part # DAC38RF82IAAV
Description  DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation
PDF  147 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF82IAAV Datasheet(HTML) 39 Page - Texas Instruments

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DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
8.3.10 SYSREF Capture Circuit
The JESD204B standard for Device Subclass 1 introduces a SYSREF signal that can be used as a global timing
reference to align the phase of the internal local multiframe clock (LMFC) and frame clock across multiple
devices. This allows the system to achieve deterministic latency and align data samples across several data
converters. The SYSREF signal accomplishes this goal by identifying a device clock edge for each chip that can
be used as an alignment reference. In particular, the LMFC and frame clock align to the device clock edge upon
which the SYSREF transition from “0” to “1” is sampled. SYSREF may be periodic, one-shot, or “gapped”
periodic and its period must be a multiple of the LMFC period.
Figure 30. SYSREF Signal Timing
With high-speed device clocks, the phase of the SYSREF signals relative to the device clock must meet the
setup/hold time requirements of each individual device clock. Historically, this has been done by controlling the
board-level routing delay and/or employing commercial clock distribution capable of generating device clocks and
SYSREF signals with programmable delays and with the option of splitting SYSREF into multiple SYSREFS,
each with its own fine-tuned delay. Since the DAC38RF82 (or DAC38RF89) supports device clock frequencies
up to 9 GHz, a SYSREF capture circuit is includes in the DAC38RF82 (or DAC38RF89) that allows a relaxation
in meeting the device clock setup and hold.
The SYSREF capture circuit provides:
•
tolerance to manufacturing and environmental variations in SYSREF phase
•
immunity to sampling errors due to setup/hold/meta-stability
•
information about phase of SYSREF relative to DAC clock inside the data converter
•
software compensation for phase misalignment due to PCB design errors
The concepts behind the SYSREF capture scheme are illustrated in Figure 31.



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