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DAC38RF82IAAV Datasheet(PDF) 8 Page - Texas Instruments |
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DAC38RF82IAAV Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 147 page  8 DAC38RF82, DAC38RF89 SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020 www.ti.com Product Folder Links: DAC38RF82 DAC38RF89 Submit Documentation Feedback Copyright © 2017–2020, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME A3 SYSREF+ I LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC synchronization. A4 SYSREF- I LVPECL SYSREF negative input, self biased, internal 100 Ω differential termination. (See the SYSREF+ description) K4 TCLK I JTAG test clock. Internal pull-down H4 TDI I JTAG test data in. Internal pull-up J4 TDO O JTAG test data out. Internal pull-up K3 TESTMODE - This pin is used for factory testing. Recommended to connect to ground for normal operation. K5 TMS I JTAG test mode select. Internal pull-up J5 TRST I JTAG test reset. Internal pull-up. Must be connected to ground if not used K6 TXENABLE I Transmit enable active high input. Internal pull-down. This pin is ORed with spi_txenable bit in JESD_FIFO register to enable analog output data transmission. To enable analog output data transmission, pull CMOS TXENABLE pin to high. To disable analog output, pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. F11, J11 VDDA1 I Analog 1 V supply voltage. Must be separated from VDDDIG1 supply for best performance. G11, H11 VDDA18 I Analog 1.8 V supply voltage. (1.8 V) D8, E8 VDDPLL1 I Analog 1 V supply for PLL. B9, B10 VDDAPLL18 I PLL analog supply voltage. (1.8 V) D9, E9 VDDAVCO18 I Analog supply voltage for VCO (1.8 V) G9, H9 VDDCLK1 I Internal clock buffer supply voltage (1 V). It is recommended to isolate this supply from VDDDIG1 and VDDA1. G8, H8 VDDL1_1 I DAC core supply voltage. (1 V) G10, H10 VDDL2_1 I DAC core supply voltage. (1 V) A5, B5, C5, D5, D7, E3, E4, E5, E6, F4, F5, G4, G5 VDDDIG1 I Digital supply voltage. (1 V). It is recommended to isolate this supply from VDDCLK1 and VDDA1. F7, H7, G6, J6 VDDE1 I Digital Encoder supply voltage (1 V). Must be separated from VDDDIG1 supply H5 VDDIO18 I Supply voltage for all digital I/O and CMOS I/O. (1.8 V) G12, H12 VDDOUT18 I DAC output supply. (1.8 V) H2, J2 VDDR18 I Supply voltage for SerDes. (1.8 V) B3, B4 VDDS18 I Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8 V) H3, J3 VDDT1 I Supply voltage for SerDes termination. (1 V) B6 VDDTX1 I Supply voltage for divided clock output. (1 V) B7 VDDTX18 I Supply voltage for divided clock output . (1.8 V) D10, E10, K10, L10 VEE18N I Analog supply voltage. (-1.8 V) L12 VOUT1+ O DAC channel 1 output. K12 VOUT1- O DAC channel 1 complementary output. D12 VOUT2+ O DAC channel 2 output. E12 VOUT2- O DAC channel 2 complementary output. D4 VSENSE O Test pin for on chip parametrics. Can be left floating. A8, A11, B8, B11, B12, F8, F9, F10, J8, J9, J10 VSSCLK - Clock ground. |
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