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DAC38RF82IAAV Datasheet(PDF) 4 Page - Texas Instruments

Part # DAC38RF82IAAV
Description  DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface, On-Chip PLL and Wide-Band Interpolation
PDF  147 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DAC38RF82IAAV Datasheet(HTML) 4 Page - Texas Instruments

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DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Product Folder Links: DAC38RF82 DAC38RF89
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Copyright © 2017–2020, Texas Instruments Incorporated
•
Changed INL typical value From: ±1 To: ±4 LSB in Electrical Characteristics - DC Specifications table............................ 10
•
Added "Reference voltage drift" to the Electrical Characteristics - DC Specifications table ................................................ 10
•
Changed Power Dissipation Test Condition From: MODE 5: dual channel, 8-bit input mode, 2x Interpolation To:
MODE 5: dual channel, 8-bit input mode, 1x Interpolation in the Electrical Characteristics - DC Specifications ................ 11
•
Changed the ILOAD values to negative for CMOS interface parameter, low-level output voltage, in the Electrical
Characteristics - Digital Specifications table......................................................................................................................... 12
•
Added 0 dBFS to the condition statement for the Electrical Characteristics - AC Specifications table ............................... 15
•
Added MIN and TYP value to maximum DAC sample rate for DAC38RF89 only in the Electrical Characteristics - AC
Specifications table............................................................................................................................................................... 15
•
Added NSD values for DAC38RF82 with on-chip PLL enabled to Electrical Characteristics - AC Specifications table...... 17
•
Changed the Isolation values in the TEST CONDITIONS, TYP value From: 74 dBc To: 82 dBc and 56 dBc To 73
dBc in the Electrical Characteristics - AC Specifications table............................................................................................. 17
•
Added Figure 16 ................................................................................................................................................................... 21
•
Added MPY value for 16.5x in the Table 4........................................................................................................................... 29
•
Changed input rate max and fdac max for 6x interpolation mode in Table 9 ..................................................................... 32
•
Changed input data rate From: 6666 MSPS To: 3333 MSPS for LMFSHd=41380, 2x interpolation in Table 9 ................ 33
•
Changed Table 12, JESD204B frame format for LMFSHd=84111 ..................................................................................... 33
•
Changed Table 14, JESD204B frame format for LMFSHd=44210 ...................................................................................... 34
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Changed Table 16, JESD204B frame format for LMFSHd = 24410 .................................................................................... 34
•
Changed Table 17, JESD204B frame format for LMFSHd = 44210 .................................................................................... 34
•
Changed Table 18, JESD204B frame format for LMFSHd = 88210 .................................................................................... 35
•
Changed Table 19, JESD204B frame format for LMFSHd = 24410 .................................................................................... 35
•
Changed Table 20, JESD204B frame format for LMFSHd=48410 ...................................................................................... 35
•
Changed Table 21, JESD204B frame format for LMFSHd = 24310 .................................................................................... 35
•
Changed Table 22, JESD204B frame format for LMFSHd = 48310 .................................................................................... 35
•
Changed Table 23, JESD204B frame format for LMFSHd = 81180 .................................................................................... 36
•
Changed Table 24, JESD204B frame format for LMFSHd = 41380 .................................................................................... 36
•
Changed Table 26, JESD204B frame format for LMFSHd = 41121 .................................................................................... 37
•
Added Table 27, JESD204B frame format for LMFSHd = 41121 ........................................................................................ 38
•
Changed Table 38 ................................................................................................................................................................ 49
•
Changed register field programming values for LMFSHd=24410, 41380, 41121 and 24310 in the Register
Programming for JESD and Interpolation Mode table.......................................................................................................... 54
•
Changed the bit positions of N_M1 register field From: 12-8 To: 4-0 in the Table 42 table ................................................ 55
•
Changed the bit positions of N_M1’ (NPRIME_M1) register field From: 4-0 To: 12-0 in the Table 42 table ....................... 55
•
Changed the description of DAC PLL alarm in Alarm Monitoring ........................................................................................ 60
•
Changed from BIST_ENA to Reserved in Table 61 ............................................................................................................ 80
•
Changed from BIST_ZERO to Reserved in Table 61 ......................................................................................................... 80
•
Changed the description of OUTSUM_SEL field in Table 69 ............................................................................................. 86
•
Changed the Description of Bit 11 From "dummy data generation" to "distortion enhancement" in Table 116 ............... 116
•
Changed the junction temp and loop filter voltage range for PLL tuning in Figure 142 ..................................................... 130



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