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TDA2SA Datasheet(PDF) 104 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 104 Page - Texas Instruments |
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104 / 427 page  104 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Terminal Configuration and Functions Copyright © 2015–2019, Texas Instruments Incorporated Table 4-7. EMIF Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL ddr1_d1 EMIF1 Data Bus IO AF26 ddr1_d2 EMIF1 Data Bus IO AG26 ddr1_d3 EMIF1 Data Bus IO AH26 ddr1_d4 EMIF1 Data Bus IO AF24 ddr1_d5 EMIF1 Data Bus IO AE24 ddr1_d6 EMIF1 Data Bus IO AF23 ddr1_d7 EMIF1 Data Bus IO AE23 ddr1_d8 EMIF1 Data Bus IO AC23 ddr1_d9 EMIF1 Data Bus IO AF27 ddr1_d10 EMIF1 Data Bus IO AG27 ddr1_d11 EMIF1 Data Bus IO AF28 ddr1_d12 EMIF1 Data Bus IO AE26 ddr1_d13 EMIF1 Data Bus IO AC25 ddr1_d14 EMIF1 Data Bus IO AC24 ddr1_d15 EMIF1 Data Bus IO AD25 ddr1_d16 EMIF1 Data Bus IO V20 ddr1_d17 EMIF1 Data Bus IO W20 ddr1_d18 EMIF1 Data Bus IO AB28 ddr1_d19 EMIF1 Data Bus IO AC28 ddr1_d20 EMIF1 Data Bus IO AC27 ddr1_d21 EMIF1 Data Bus IO Y19 ddr1_d22 EMIF1 Data Bus IO AB27 ddr1_d23 EMIF1 Data Bus IO Y20 ddr1_d24 EMIF1 Data Bus IO AA23 ddr1_d25 EMIF1 Data Bus IO Y22 ddr1_d26 EMIF1 Data Bus IO Y23 ddr1_d27 EMIF1 Data Bus IO AA24 ddr1_d28 EMIF1 Data Bus IO Y24 ddr1_d29 EMIF1 Data Bus IO AA26 ddr1_d30 EMIF1 Data Bus IO AA25 ddr1_d31 EMIF1 Data Bus IO AA28 ddr1_ecc_d0 EMIF1 ECC Data Bus IO W22 ddr1_ecc_d1 EMIF1 ECC Data Bus IO V23 ddr1_ecc_d2 EMIF1 ECC Data Bus IO W19 ddr1_ecc_d3 EMIF1 ECC Data Bus IO W23 ddr1_ecc_d4 EMIF1 ECC Data Bus IO Y25 ddr1_ecc_d5 EMIF1 ECC Data Bus IO V24 ddr1_ecc_d6 EMIF1 ECC Data Bus IO V25 ddr1_ecc_d7 EMIF1 ECC Data Bus IO Y26 ddr1_dqm0 EMIF1 Data Mask O AD23 ddr1_dqm1 EMIF1 Data Mask O AB23 ddr1_dqm2 EMIF1 Data Mask O AC26 ddr1_dqm3 EMIF1 Data Mask O AA27 ddr1_dqm_ecc EMIF1 ECC Data Mask O V26 ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AH25 ddr1_dqsn0 Data strobe 0 invert IO AG25 |
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