TDA2SXABC datasheet(158/427 Pages) TI2

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158

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Specifications

Table 5-9. Maximum Supported Frequency (continued)

Module

Clock Sources

Instance Name

Input Clock Name

Clock

Type

Max. Clock

Allowed (MHz)

PRCM Clock Name

PLL / OSC /

Source Clock

Name

PLL / OSC /

Source Name

USB_PHY2_CORE USB2PHY2_WKUP

_CLK

Func

0.032

COREAON_32K_

GFCLK

SYS_CLK1/610

OSC1

USB_PHY3_CORE

USB3PHY_WKUP

_CLK

Func

0.032

COREAON_32K_

GFCLK

SYS_CLK1/610

OSC1

5.6

Power Consumption Summary

NOTE

Maximum power consumption for this SoC depends on the specific use conditions for the

end system. Contact your TI representative for assistance in estimating maximum power

consumption for the end system use case.

5.7

Electrical Characteristics

NOTE

The data specified in Section 5.7.1 through Section 5.7.12 are subject to change.

NOTE

The interfaces or signals described in Section 5.7.1 through Section 5.7.12 correspond to the

interfaces or signals available in multiplexing mode 0 (Function 1).

All interfaces or signals multiplexed on the balls described in these tables have the same DC

electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which

case different DC electrical characteristics are specified for the different multiplexing modes

(Functions).

5.7.1

LVCMOS DDR DC Electrical Characteristics

Table 5-10 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.

NOTE

For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control

Module of the Device TRM.

Table 5-10. LVCMOS DDR DC Electrical Characteristics

PARAMETER

MIN

NOM

MAX

UNIT

Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[0], ddr1_cke,

ddr1_odt[0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc, ddr2_d[31:0], ddr2_a[15:0], ddr2_dqm[3:0],

ddr2_ba[2:0], ddr2_csn[0], ddr2_cke, ddr2_odt[0], ddr2_casn, ddr2_rasn, ddr2_wen, ddr2_rst;

Balls: AA28 / AA25 / AA26 / Y24 / AA24 / Y23 / Y22 / AA23 / Y20 / AB27 / Y19 / AC27 / AC28 / AB28 / W20 / V20 / AD25 / AC24 / AC25 /

AE26 / AF28 / AG27 / AF27 / AC23 / AE23 / AF23 / AE24 / AF24 / AH26 / AG26 / AF26 / AF25 / AD18 / AE17 / AF18 / AC21 / AD22 /

AD21 / AE22 / AF22 / AE21 / AE21 / AH22 / AF21 / AB19 / AC20 / AC19 / AD20 / AA27 / AC26 / AB23 / AD23 / AB18 / AE18 / AF17 /

AH23 / AG22 / AE20 / AC18 / AF20 / AH21 / AG21 / Y26 / V25 / V24 / Y25 / W23 / W19 / V23 / W22 / V26 / M26 / M25 / M24 / M23 / L28 /

L25 / L26 / L27 / J20 / K22 / J23 / L24 / L23 / K21 / K20 / L22 / J24 / J26 / J25 / G26 / H26 / H24 / H25 / H23 / E28 / E27 / F27 / F26 / F24 /

F25 / G25 / E26 / U22 / R22 / T22 / N28 / P26 / N23 / N27 / P27 / N20 / P25 / P22 / P23 / R27 / R28 / R26 / R25 / M22 / K23 / G24 / F28 /

U26 / U27 / U23 / P24 / U24 / R23 / U28 / T23 / U25 / R24;

Driver Mode

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