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TDA2SXABC Datasheet(PDF) 159 Page - Texas Instruments |
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TDA2SXABC Datasheet(HTML) 159 Page - Texas Instruments |
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159 / 427 page  159 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Specifications Copyright © 2015–2019, Texas Instruments Incorporated Table 5-10. LVCMOS DDR DC Electrical Characteristics (continued) PARAMETER MIN NOM MAX UNIT VOH High-level output threshold (IOH = 0.1 mA) 0.9*VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1*VDDS V CPAD Pad capacitance (including package capacitance) 3 pF ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V DDR2 VREF+0.125 VDDS+0.3 VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V DDR2 -0.3 VREF-0.125 VCM Input common-mode voltage VREF -10%vdds VREF+ 10%vdds V CPAD Pad capacitance (including package capacitance) 3 pF Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr2_dqs[3:0], ddr2_dqsn[3:0], ddr2_ck, ddr2_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc Bottom Balls: Y28 / AD27 / AE27 / AH25 / Y27 / AD28 / AE28 / AG25 / AG24 / AH24 / M28 / K27 / H27 / G28 / M27 / K28 / H28 / G27 / T28 / T27 / V27 / V28 Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9*VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1*VDDS V CPAD Pad capacitance (including package capacitance) 3 pF ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold DDR3/DDR3L VREF+0.1 VDDS+0.2 V DDR2 VREF+0.125 VDDS+0.3 VIL Low-level input threshold DDR3/DDR3L -0.2 VREF-0.1 V DDR2 -0.3 VREF-0.125 VCM Input common-mode voltage VREF -10%vdds VREF+ 10%vdds V CPAD Pad capacitance (including package capacitance) 3 pF Differential Receiver Mode VSWING Input voltage swing DDR3/DDR3L 0.2 vdds+0.4 V DDR2 0.25 vdds+0.6 VCM Input common-mode voltage VREF -10%vdds VREF+ 10%vdds |
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