LM67660 datasheet(21/66 Pages) TI2

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As shown in Table 7-2, if MODE/SYNC is grounded or driven to a logic low, the converter operates in AUTO

mode. If the pin is tied to VCC or driven to a logic high, or synchronized to an external clock source, the

converter operates in FPWM mode.

Table 7-2. Mode Selection

MODE/SYNC

MODE

DYNAMIC MODE CHANGE

Tied to PGND or driven low

AUTO

Enabled

Tied to VCC or driven high (> 2.5V above PGND)

FPWM

External clock signal applied

Transitioning the device from AUTO to FPWM mode requires driving the pin from low to high or applying a

synchronization signal. Transitioning from FPWM to AUTO mode requires driving the pin from high to low or

stopping the synchronization signal.

Note

Changing the mode of operation or synchronizing the device to an external clock is possible only after

start-up, once PG transitions high.

7.3.6.1 Clock Synchronization

Use the MODE/SYNC to synchronize the internal oscillator to an external clock signal running between 300kHz

and 2.2MHz. The amplitude of the external clock must meet the SYNC input thresholds, VSYNC(IH) and VSYNC(IL),

to reliably trigger the internal synchronization pulse detector. The minimum SYNC ON and OFF pulse durations

must exceed tSYNC-ON(min) and tSYNC-OFF(min), respectively.

Note that an external clock signal can only be applied after power up, when PG transitions to high. If applied

before power up (or during pin detection), the LM65680/60/40 can not detect the clock signal.

VSYNC(IH)

tSYNC-LOW(min)

tSYNC-HIGH(min)

VSYNC(IL)

VSYNC

Figure 7-4. Typical SYNC Waveform With Conditions Required for Clock Signal Detection

7.3.6.2 Clock Locking

Upon detection of a valid synchronization signal, the LM65680/60/40 inititates a clock locking procedure. After

approximately 2048 pulses, the internal oscillator frequency changes to the frequency of the synchronization

signal. While the frequency adjusts suddenly, the LM65680/60/40 maintain the phase such that the clock cycle

lying between operation at the free-running and synchronization frequencies is of intermediate length. There are

no very long or very short pulses. Once the frequency locks, the phase adjusts over tens of cycles such that

rising synchronization edges correspond to switch-node rising pulses. Refer to Figure 7-5.

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LM65680

SNVSCF2 – NOVEMBER 2025

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