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AD9785 Datasheet(PDF) 4 Page - Analog Devices |
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AD9785 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 64 page  AD9785/AD9787/AD9788 Rev. 0 | Page 4 of 64 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input VIN Logic High 2.0 V Input VIN Logic Low 0.8 V LVDS INPUT (SYNC_I+, SYNC_I−) SYNC_I+ = V1A, SYNC_I− = V1B Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH –100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate (fSYNC_I = fDATA) 30 MHz Setup Time, SYNC_I to DAC Clock 0.45 ns Hold Time, SYNC _I to DAC Clock 0.25 ns LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination Output Voltage High, VOA or VOB 825 1575 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, RO 80 100 120 Ω DAC CLOCK INPUT (REFCLK+, REFCLK–) Differential Peak-to-Peak Voltage 400 800 1600 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate DVDD18 = 1.8 V ± 5% 800 MHz DVDD18 = 1.9 V ± 5% 900 MHz MAXIMUM INPUT DATA RATE 1× Interpolation 250 MSPS 2× Interpolation 250 MSPS 4× Interpolation DVDD18 = 1.8 V ± 5% 200 MSPS DVDD18 = 1.9 V ± 5% 225 MSPS 8× Interpolation DVDD18 = 1.8 V ±5% 100 MSPS DVDD18 = 1.9 V ± 5% 112.5 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High 12.5 ns Minimum Pulse Width Low 12.5 ns Setup Time, SPI_SDIO to SCLK 2.8 ns Hold Time, SPI_SDIO to SCLK 0.0 ns Setup Time, SPI_CSB to SCLK 3.0 ns Data Valid, SPI_SDO to SCLK 10.0 ns INPUT DATA All modes, −40°C to +85°C1 Setup Time, Input Data to DATACLK 460 ns Hold Time, Input Data to DATACLK −1.5 ns Setup Time, Input Data to REFCLK −0.25 ns Hold Time, Input Data to REFCLK 2.4 ns |
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