LTC1064 datasheet(11/30 Pages) AD

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LTC1068 Series

1068fc

PIN FUNCTIONS

BLOCK DIAGRAM

path. A 200Ω resistor between clock source and Pin 11

will slow down the rise and fall times of the clock to further

reduce charge coupling (Figures 1 and 2).

Output Pins

Each 2nd order section of an LTC1068 device has three

outputs that typically source 17mA and sink 6mA. Driv-

ing coaxial cables or resistive loads less than 20k will

degrade the total harmonic distortion performance of

any filter design. When evaluating the distortion or noise

performance of a particular filter design implemented with

a LTC1068 device, the final output of the filter should be

buffered with a wideband, noninverting high slew rate

amplifier (Figure 3).

Inverting Input Pins

These pins are the inverting inputs of internal op amps

and are susceptible to stray capacitive coupling from low

impedance signal outputs and power supply lines.

In a printed circuit layout any signal trace, clock source

trace or power supply trace should be at least 0.1 inches

away from any inverting input pins

Summing Input Pins

These are voltage input pins. If used, they should be driven

with a source impedance below 5k. When they are not

used, they should be tied to the analog ground pin.

The summing pin connections determine the circuit to-

pology (mode) of each 2nd order section. Please refer to

Modes of Operation.

Figure 3. Wideband Buffer

–

LT®1354

1068 F03

RA*

RB*

V+ (8)

CLK (21)

V– (23)

NC (6)

NC (9)

NC (20)

NC (22)

AGND (7)

1068 BD

–

HPC/NC

(27)

BPC

(26)

LPC

(25)

HPB/NB

(2)

BPB

(3)

LPB

(4)

*THE RATIO RA/RB VARIES ±2%

BPA

(12)

LPA

(11)

INV A

(14)

AGND

(7)

INV C

(28)

HPA/NA

(13)

+ Σ

(10)

–

INV D

(15)

INV B

(1)

HPD/ND

(16)

–

(5)

–

(24)

–

(19)

BPD

(17)

LPD

(18)

PIN 28-LEAD SSOP PACKAGE

DEVICE

LTC1068

LTC1068-200

LTC1068-25

LTC1068-50

10k

11.3k

10k

8.6k

LTC1064 Datasheet(PDF) 11 Page - Analog Devices

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