CLC016 datasheet(15/19 Pages) NSC

15 / 19 page

Product Description (Continued)

Terminating Physically Separated Outputs

When the circuit design requires the outputs to be routed to

separate locations, the recommended interface is depicted

in Figure 20. Choose the resistors for an equivalent 75

Ω

termination of the cable impedance (or other cable charac-

teristic impedance, as appropriate).

CONTROL LINE INTERFACES

The use of the CLC016 with +5V supplies allows the control

lines to interface to standard TTL logic signals. Operating the

CLC016 at −5.2V requires level-shifting circuits for the con-

trol line inputs. Refer to the Static Performance section of

the Electrical Characteristics page for required input volt-

age levels.

POWER CONSUMPTION

The power supply current given in the Electrical Character-

istics table includes the current required for both the clock

and data output buffers to drive a 75

Ω load to ECL swings.

TYPICAL APPLICATIONS

The CLC016 was designed as one of a series of data

transmission support chips. The CLC016 is recommended

for a wide variety of clock and data recovery applications that

fit within its range of data rates.

Serial Data Transmission over Cable

Serial data transmission is common for all types of commu-

nication channels where the data is sent over coaxial or

twisted pair cable. Figure 21 shows a typical connection

using a CLC006 driver chip, CLC014 Adaptive Cable Equal-

izer, and the CLC016 Data Retiming PLL. The CLC016

extracts the clock and retimes the data from the serial bit

stream.

The components recommended in Figure 21 support the

four common data rates specified in SMPTE 259M.

ESD

The CLC016 is a CMOS chip. Operators are cautioned to

use grounding straps when handling.

MEASUREMENTS & EVALUATION

When evaluating the CLC016 Data Retimer, it is recom-

mended that you solder the part to the board or use a

leadless chip carrier socket. Probing with capacitive probes

will disturb the CLC016 performance. When probing the

signal levels use a 1 pF capacitance probe with a 500

Ω tip.

The block diagram below shows a simple method of mea-

suring the clock to eye pattern jitter. Use of the CLC016

evaluation board is recommended for jitter evaluation. It also

provides a good reference for a user’s circuit board design.

The plot in Figure 23 shows a histogram of the jitter and

where the measurements were taken.

10008731

FIGURE 19. Differential Source-

Terminated Output Interface

10008732

FIGURE 20. Load Terminated Output Interface

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