CLC016 datasheet(17/19 Pages) NSC

17 / 19 page

Product Description (Continued)

PCB LAYOUT RECOMMENDATIONS

Printed circuit board layout affects the performance of the

CLC016. The following are PCB layout rules for the CLC016:

Use a ground plane.

De-couple V

CC/V EE power pins with 0.01 µF ceramic

capacitors placed

≤0.1” (3mm) from the power pins and

6.8 µF tantalum capacitors.

For long signal runs, match transmission lines to the

desired characteristic impedance for the input and out-

put lines.

Remove ground plane 0.025” (0.06mm) from all pads.

Remove ground plane from the area around the loop

filter and frequency selection resistors.

Keep digital and analog lines sufficiently away from loop

filter or frequency selection resistors.

Avoid the use of sockets in production boards.

In proto-boards use a low-profile, low impedance, type

socket.

EVALUATION BOARD

Evaluation boards are available for a nominal charge that

demonstrate the basic operation of the SDI/SDV/SDH de-

vices. The evaluation boards can be ordered through Nation-

al’s Distributors. Supplies are limited, please check for cur-

rent availability.

The SD901EVK SMPTE 259M Receiver evaluation kit pro-

vides an operating environment in which the data retimer

can be evaluated by system / hardware designers. The

evaluation board has all the needed circuitry and connectors

for easy connection and checkout of the device circuit op-

tions as discussed in the CLC016 datasheet. A schematic,

parts list and pictorial drawing are provided with the board.

From the WWW, the following information may be viewed /

downloaded

for

most

evaluation

boards:

www.national.com/appinfo/interface

•

Device Datasheet and / or EVK User Manual

•

View a picture of the EVK

•

View the EVK Schematic

•

View the top assembly drawing and BOM

•

View the bottom assembly drawing and BOM

10008735

FIGURE 23. Typical Jitter Histogram

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