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DA9131 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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DA9131 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 59 page ![]() DA9131 Datasheet R16DS0576EJ0300 Rev.03.00 July 18, 2025 CFR0011-120-00 Page 39 Bit Type Symbol Description [3:0] RW CH2_EN_DLY Delay for CH2 enable. Active with GPIO configured as EN1&EN2 control and IC_EN control. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 0 0x1 0.5 ms 0x2 1.0 ms 0x3 1.5 ms 0x4 2.0 ms 0x5 2.5 ms 0x6 3.0 ms 0x7 3.5 ms 0x8 4.0 ms 0x9 4.5 ms 0xA 5.0 ms 0xB 5.5 ms 0xC 6.0 ms 0xD 6.5 ms 0xE 7.0 ms 0xF 7.5 ms Table 35. SYS_CONFIG_2 (0x0D) Bit Type Symbol Description [6:5] RW OC_LATCHOFF Over-current latch -off setting. BUCK shut-down after OCP for 8 µs/1 ms/3 ms unless disable setting. IRQ is generated unless IRQ is masked. Value Description 0x0 Latch off disable 0x1 Latch off after 8 µs of OCP signal 0x2 Latch off after 1 ms of OCP signal 0x3 Latch off after 3 ms of OCP signal [4] RW OC_DVC_MASK Over-current event (IRQ and latch -off feature) mask during DVC ramp -up and ramp-down for both CH1 and CH2 [3:2] RW PG_DVC_MASK Power-good mask during DVC for both CH1 and CH2 Value Description 0x0 No mask 0x1 Mask as not power-good during DVC 0x2 Mask as power-good during DVC 0x3 Reserved |
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