DS1302 Trickle-Charge Timekeeping Chip

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CLOCK/CALENDAR BURST MODE

The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar

registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0.

If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to

any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in

burst mode.

At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time

information is read from these secondary registers, while the clock may continue to run. This eliminates the need to

re-read the registers in case of an update of the main registers during a read.

RAM

The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.

RAM BURST MODE

The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively

read or written (see Table 2) starting with bit 0 of address 0.

REGISTER SUMMARY

A register data format summary is shown in Table 2.

CRYSTAL SELECTION

A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for

layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks.

Figure 5. Data Transfer Summary

A1

A2

A3

1

CE

SCLK

I/O

D1

D2

D3

D4

D5

D6

D7

D0

SINGLE-BYTE READ

A1

A2

A3

1

CE

SCLK

I/O

D1

D2

D3

D4

D5

D6

D7

D0

SINGLE-BYTE WRITE

NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST.