AD9879BSZ datasheet(18/32 Pages) AD

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AD9879

Rev. A | Page 18 of 32

The default value for the clamp level control value is 0x20. This

results in an ADC output clamp level offset of 512 LSBs. The

valid programming range for the clamp level control value is

from 0x16 to 0x127.

Bit 0: Send 10-Bit ADC Data Only

When this bit is set high, the device enters a nonmultiplexed

mode and only the data from the 10-bit ADC is sent to the IF

[11:0] digital output port.

Bit 1: Send 12-Bit ADC Data Only

When this bit is set high, the device enters a nonmultiplexed

mode and only data from the 12-bit ADC is sent to the IF [11:0]

digital output port.

Bit 3: Enable 7-Bits, IQ ADC

When this bit is active, the IQ ADC is put into 7-bit mode. In

this mode, the full-scale input range is 2 Vppd. When this bit is

set inactive, the IQ ADC is put into 6-bit mode and the full-

scale input voltage range is 1 Vppd.

Bit 4: Power-Down RXSYNC and IQ ADC Clocks

Setting this bit to 1 powers down the IQ ADC’s sampling clock

and stops the RXSYNC output pin. It can be used for additional

power saving on top of the power-down selections in Register 0x02.

Bit 5: Rx Port Fast Edge Rate

Setting this bit to 1 increases the output drive strength of all

digital output pins, except MCLK, REFCLK, Σ-Δ_OUT, and

FLAG1. These pins always have high output drive capability.

Bit 7: ADC Clocked Direct from OSCIN

When set high, the input clock at OSCIN is used directly as the

ADC sampling clock. When set low, the internally generated

master clock, MCLK, is divided by two and used as the ADC

sampling clock. Best ADC performance is achieved when the

ADCs are sampled directly from fOSCIN using an external crystal

or low jitter crystal oscillator.

Bits 0–3: Version

The die version of the chip can be read from this register.

LSBs

This register accommodates two LSBs for both frequency

tuning words. For more information, see the description in the

Registers 0X10–0X17—Carrier Frequency Tuning section.

Bits 0–3: DAC Fine Gain Control

This bit field sets the DAC gain if the Tx Path AD8321/AD8323

gain control select bit (Register F, Bit 3) is set to 0. The DAC

gain can be set from 0.0 dB to 7.5 dB in increments of 0.5 dB.

Table 6 details the programming.

Table 6. DAC Gain Control

Bits [3:0]

DAC Gain

0000

0.0 dB (default)

0001

0.5 dB

0010

1.0 dB

0011

1.5 dB

....

1110

7.0 dB

1111

7.5 dB

Bit 0: Single-Tone Tx Mode

Active high configures the AD9879 for single-tone applications

such as FSK. The AD9879 supplies a single frequency output as

determined by the frequency tuning word selected by the active

profile. In this mode, the TXIQ input data pins are ignored but

should be tied to a valid logic voltage level. The default value is

0 (inactive).

Bit 1: Spectral Inversion Tx

When set to 1, inverted modulation is performed.

MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)]

(10)

The default is logic low, noninverted modulation.

MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)]

(11)

Bit 2: Tx Path Bypass Sinc–1 Filter

Setting this bit high bypasses the digital inverse sinc filter of the

Tx path.

Bit 3: Tx Path AD8322/AD8327 Gain Control Mode

This bit changes the manner in which transmit gain control is

performed. Typically either AD8321/AD8323 (default 0) or

AD8222/AD8327 (default 1) variable gain cable drivers are

programmed over the chip’s 3-wire CA interface. The Tx gain

control select changes the interpretation of the bits in

Registers 0x13 and 0x17. See the Cable Driver Gain Control

section.

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