GD32H757VMT7 datasheet(123/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

122

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

0x800 after factory

calibration

VREFP = 1.8 V

—

±8

Gain(2)

Gain error

DAC output buffer ON

—

±0.5

DAC output buffer OFF

—

±0.5

(1)

Value guaranteed by design, not 100% tested in production.

(2)

Value guaranteed by characterization, not 100% tested in production.

4.22.

I2C characteristics

Table 4-55. I2C characteristics(1)(2)

Symbol

Parameter

Conditions

Standard mode

Fast mode

plus

Unit

Min

Max

Min

Max

Min

Max

tSCL(H)

SCL clock high time

—

4.0

—

0.6

—

0.2

—

μs

tSCL(L)

SCL clock low time

—

4.7

—

1.3

—

0.5

—

μs

tSU(SDA)

SDA setup time

—

250

—

100

—

tH(SDA)

SDA data hold time

—

0(3)

3450

900

450

tR(SDA/SCL)

SDA and SCL rise

time

—

1000

—

300

—

120

tF(SDA/SCL)

SDA and SCL fall

time

—

300

—

300

—

120

tH(STA)

Start condition hold

time

—

4.0

—

0.6

—

0.26

—

μs

tSU(STA)

Repeated Start

condition setup time

—

4.7

—

0.6

—

0.26

—

μs

tSU(STO)

Stop condition setup

time

—

4.0

—

0.6

—

0.26

—

μs

tBUFF

Stop to Start

condition time (bus

free)

—

4.7

—

1.3

—

0.5

—

μs

(1)

Value guaranteed by design, not 100% tested in production.

(2)

To ensure the standard mode I2C frequency, fPCLK1 must be at least 2 MHz. To ensure the fast mode I2C

frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode plus I2C frequency, fPCLK1 must be at least a

multiple of 10 MHz.

(3)

The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the

falling edge of SCL.

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