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GD32H757VMT7 Datasheet(PDF) 125 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757VMT7 Datasheet(HTML) 125 Page - GigaDevice Semiconductor (Beijing) Inc. |
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125 / 151 page  GD32H757xx Datasheet 124 Figure 4-8. SPI timing diagram - master mode SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MISO MOSI D[0] LF=1,FF16=0 D[7] D[7] tSCK tSCK(H) tH(MI) tSU(MI) tV(MO) tH(MO) tSCK(L) D[0] Figure 4-9. SPI timing diagram - slave mode SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) MISO MOSI tA(SO) tSU(NSS) NSS tV(SO) tH(SI) tSU(SI) tDIS(SO) tH(NSS) tSCK tSCK(H) tSCK(L) tH(SO) D[0] D[7] D[0] D[7] 4.24. OSPI characteristics Table 4-58. Standard OSPI characteristics(1) Symbol Parameter Conditions Min Typ Max Unit SDR mode fSCK SCK clock frequency — — — 100 MHz |
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