GD32H757VMT7 datasheet(121/151 Pages) GIGADEVICE

121 / 151 page

GD32H757xx Datasheet

120

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

OFF

RBON(1)

Output impedance sample

and hold mode, output

buffer ON

DAC output buffer ON

—

1.5

kΩ

RBOFF(1)

Output impedance sample

and hold mode, output

buffer OFF

DAC output buffer OFF

—

1.5

CLOAD(1)

Capacitive load

DAC output buffer ON

—

CSH(1)

Sample and Hold mode

—

0.1

µF

VDAC_OUT

Voltage on DAC_OUT

output

DAC output buffer ON

0.2

—

VDDA-

0.2

DAC output buffer OFF

—

VDDA-

1LSB

tSETTLING(1)

Settling time (full scale: for

a 12-bit code transition

between the lowest and the

highest input codes when

DAC_OUT reaches the

final value of ±0.5 LSB,

±1 LSB, ±2 LSB, ±4 LSB,

± 8 LSB)

Normal mode, DAC

output buffer ON, CL

≤ 50 pF,

RL ≥ 5 kΩ

±1 LSB

—

1.06

—

µs

±2 LSB

—

0.38

—

±4 LSB

—

0.33

—

±8 LSB

—

0.30

—

Normal mode, DAC output buffer

OFF, ±1LSB CL = 10 pF

—

1.95

2.5

tWAKEUP(1)

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until

the final value of ±1 LSB is

reached

Normal mode, DAC output buffer

ON, CL ≤ 50 pF, RL = 5 kΩ

—

µs

Normal mode, DAC output buffer

OFF, CL ≤ 10 pF

—

PSRR

Power supply rejection

ratio(to VDDA)

No RLoad, CLOAD = 50 pF

—

tSAMP(1)

Sampling time in Sample

and Hold mode

CL = 100 nF

(code transition between

the lowest input code and

the highest input code

when DAC_OUT reaches

the ±1LSB final value)

MODE<2:0>_V12 = 100 / 101

(BUFFER ON)

—

0.8

1.1

MODE<2:0>_V12 = 110 (BUFFER

OFF)

—

9.20

10.5

MODE<2:0>_V12 = 111 (INTERNAL

BUFFER OFF)

—

1.75

2.30

µs

CIint

Internal sample and hold

capacitor

—

5.5

8.5

tTRIM

Middle code offset trim time

Minimum time to verify the each

code

100

—

µs

Voffset

Middle code offset for 1

VREFP = 3.6 V

—

870

—

µV

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