14

Proprietary to OmniVision Technologies

Version 1.3, January 15, 2003

OV7640/OV7140

CMOS VGA (640 x 480) CAMERACHIP™

Omni ision

73

HSDYF

50

RW

Data Format – HSYNC Falling Edge Delay LSB

HSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0]

• Range 000 to 762 pixel delays

74

COMM

20

RW

Common Mode Control M

Bit[7]:

Reserved

Bit[6:5]:

AGC – Maximum Gain Select

00:

+6db

01:

+12db

10:

+6db

11:

+18db

Bit[4:0]:

Reserved

75

COMN

02

RW

Common Mode Control N

Bit[7]:

Output Format – Vertical Flip Enable

Bit[6:0]:

Reserved

76

COMO

01

RW

Common Mode Control O

Bit[7:6]:

Reserved

Bit[5]:

Standby Mode Enable

Bit[4:3]:

Reserved

Bit[2]:

SCCB – Tri-State Enable – VSYNC, HREF and PCLK

Bit[1:0]:

Reserved

77-7D

RSVD

XX

–

Reserved

7E

AVGY

00

RW

AEC – Digital Y/G Channel Average

(Automatically updated by AGC/AEC, user can only read the values)

7F

AVGR

00

RW

AEC – Digital R/V Channel Average

(Automatically updated by AGC/AEC, user can only read the values)

Note: This function is not available on the B&W OV7140.

80

AVGB

00

RW

AEC – Digital B/U Channel Average

(Automatically updated by AGC/AEC, user can only read the values)

Note: This function is not available on the B&W OV7140.

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

Table 5

SCCB Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description