AD1888

Rev. A | Page 12 of 32

Table 7. Reset Register (Index 00h)

Reg No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

00h

Reset

X

SE4

SE3

SE2

SE1

SE0

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

0090h

All registers not shown and bits containing an X are assumed to be reserved.

Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration).

Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement.

ID[9:0] Identify Capability. The ID decodes the capabilities of AD1888 based on the following:

Bit = 1

Function

AD1888

ID0

Dedicated Mic PCM In Channel

0

ID1

Modem Line Codec Support

0

ID2

Bass and Treble Control

0

ID3

Simulated Stereo (Mono to Stereo)

0

ID4

Headphone Out Support

1

ID5

Loudness (Bass Boost) Support

0

ID6

18-Bit DAC Resolution

0

ID7

20-Bit DAC Resolution

1

ID8

18-Bit ADC Resolution

0

ID9

20-Bit ADC Resolution

0

SE[4:0] Stereo Enhancement. The AD1888 does not provide hardware 3D stereo enhancement. (All bits are zeros.)

Table 8. Master Volume Register (Index 02h)

Reg

No.

Name

D15

D14

D131

D12

D11

D10

D9

D8

D7

D6

D4

D3

D2

D1

D0

Default

02h

Master

Volume

MM

X

LMV5

LMV4

LMV3

LMV2

LMV1

LMV0

MMRM2

X

RMV5

RMV4

RMV3

RMV2

RMV1

RMV0

8000h

generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set

to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback, all lower five bits will read 1s whenever these bits are set to 1.

MSPLT is not set, Bit D7 has no effect. All registers not shown and bits containing an X are assumed to be reserved.

Note that depending on the state of the AC97NC bit in Register 0x76, this register has the following additional functionality:

For AC97NC = 0, the register controls the Line_out output Attenuators only.

For AC97NC = 1, the register controls the Line_out, Center, and LFE output Attenuators.

RMV[5:0]

Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a

maximum attenuation of 46.5 dB.

MMRM

Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the MM

bit. Otherwise this bit will always read 0 and will have no effect when set to 1.

LMV[5:0]

Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum

attenuation of 46.5 dB.

MM

Headphones Volume Mute. When this bit is set to 1, both the left and the right channels are muted, unless the MSPLT bit in

Register 76h is set to 1.