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PRELIMINARY
Clock Generator for Intel® Calistoga Chipset
CY28443
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07716 Rev *C
Revised October 17, 2005
Features
• Compliant to Intel® CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96-MHz differential dot clock
• 27-MHz Spread and Non-spread video clock
• 48-MHz USB clocks
• SRC clocks independently stoppable through
CLKREQ#[A:B]
• 96/100-MHz Spreadable differential video clock
• 33-MHz PCI clock
• Buffered Reference Clock 14.318-MHz
• Low-voltage frequency select input
•I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP/TSSOP packages
CPU
SRC
PCI
REF
DOT96
USB_48M
LCD
27M
x2 / x3
x5/6/7
x6
x 2
x 1
x 1
x1
x2
VDD
1
56
PCI2/SEL_CLKREQ
VSS
2
55
PCI_STP#
PCI3
3
54
CPU_STP#
PCI4
4
53
REF0/FSC
PCI5/FCTSEL1
5
52
REF1/FCTSEL0
VSS
6
51
VSS
VDD
7
50
XIN
ITP_SEL/PCIF0
8
49
XOUT
PCIF1
9
48
VDD
VTT_PWRGD#/PD
10
47
SDATA
VDD
11
46
SCLK
FSA /48M
12
45
VSS
VSS
13
44
CPUT0
DOT96T/27M non Spread
14
43
CPUC0
DOT96C/27M Spread
15
42
VDD
FSB
16
41
CPUT1
SRCT0/100MT_SST
17
40
CPUC1
SRCC0/100MC_SST
18
39
IREF
SRCT2
19
38
VSSA
SRCC2
20
37
VDDA
VDD
21
36
SRCT11/CPUT2_itp
SRCT3
22
35
SRCC11/CPUC2_itp
SRCC3
23
34
VDD
SRCT4
24
33
SRCT9/CLKREQA
SRCC4
25
32
SRCC9/CLKREQB
SRCT5 _SATA
26
31
SRCT8
SRCC5_SATA
27
30
SRCC8
VDD
28
29
VSS
Pin Configuration
Block Diagram
IREF
VDD
REF[0:1]
VDD
CPUT2_ITP/SRCT11
CPUC2_ITP/SRCC11
VDD
Divider
Divider
Divider
14.318MHz
Crystal
CPU
PLL
LVDS
PLL
Fixed
PLL
PLLReference
XIN
XOUT
PCI_STP#
FS[C:A]
VTT_PWRGD#/PD
CPUT[0:1]
CPUC[0:1]
SRCT([2:5],[8:9])
VDD
PCI[3:5]
VDD
PCIF[0:1]
VDD_PCI
CPU_STP#
CLKREQ[A:B]#
VDD
FCTSEL1
SEL_CLKREQ
ITP_SEL
SRCC([2:5],[8:9])
48M
VDD48
SRCT0/100MT_SST
SRCC0/100MC_SST
I2C
Logic
SDATA
SCLK
27MNon-spread
VDD48
Divider
27M
PLL
27MSpread
VDD48
VDD48
DOT96T
DOT96C