AD9960

Rev. 0 | Page 6 of 12

DIGITAL SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%.

Table 5. Digital Logic Levels

Parameter

Min

Typ

Max

Unit

CMOS LOGIC INPUTS

High Level Input Voltage

DRVDD – 0.7

V

Low Level Input Voltage

0.4

V

Input Leakage Current

12

μA

Input Capacitance

3

pF

CMOS LOGIC OUTPUTS (CLOAD = 5 pF)

High Level Output Voltage (IOH = 1 mA)

DRVDD – 0.7

V

Low Level Output Voltage (IOH = 1 mA)

0.4

V

Output Rise/Fall Time (High Strength Mode and CLOAD = 5 pF)

0.7/0.7

ns

Output Rise/Fall Time (Low Strength Mode and CLOAD = 5 pF)

1.0/1.0

ns

RESET

Minimum Low Pulse Width (Relative to fADC)

1

Clock cycles

Table 6. CLKIN Timing Specifications

Parameter

Min

Typ

Max

Unit

INPUT CLOCK

CLKIN Clock Rate with 2× CLK Multiplier

16

32

MHz

CLKIN Clock Rate without 2× CLK Multiplier

4

64

MHz

CLKIN Pulse Width High

12.5

ns

CLKIN Pulse Width Low

12.5

ns

Table 7. ADIO Port Timing Specifications

Parameter

Min

Typ

Max

Unit

READ OPERATION1

Output Data Rate

2

64

MSPS

Three-State Output Enable Time (tPZL)

3

ns

Three-State Output Disable Time (tPLZ)

3

ns

Rx Data Valid Time (tVT)

1.5

ns

Rx Data Output Delay (tOD)

4

ns

WRITE OPERATION

Tx Data Setup Time (tDS)

1

ns

Tx Data Hold Time (tDH)

2.5

ns

Latch Enable Time (tEN)

3

ns

Latch Disable Time (tDIS)

3

ns

1 CLOAD = 5 pF for digital data outputs.