TPS62350 datasheet(28/45 Pages) TI

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Slave Address

R/W

Data

A = Acknowledge

S = START condition

Sr = REPEATED START condition

P = STOP condition

From Master to TPS6235x

From TPS6235x to Master

“0” Write

Slave Address

R/W

“1” Read

HS-MASTERCODE

R/W

DATA

A/A

”0” (write)

DataTransferred

(nxBytes+ Acknowledge)

A Sr SLAVE ADDRESS

HSModeContinues

F/SMode

HSMode

F/SMode

Sr Slave Address

Slave Address Byte

TPS62350, TPS62351

TPS62352, TPS62353

TPS62354, TPS62355, TPS62356

SLVS540D – MAY 2006 – REVISED OCTOBER 2007

Figure 50. "Read" Data Transfer Format in F/S-Mode

Figure 51. Data Transfer Format in H/S-Mode

MSB

LSB

The slave address byte is the first byte received following the START condition from the master device. The first

five bits (MSBs) of the address are factory preset to 10010. The next two bits (A1, A0) of the address are device

option dependent. For example, TPS62350 is factory preset to 00 and TPS62351 is preset to 10. Up to 4

TPS62350 type of devices can be connected to the same I2C-Bus. See the ordering information table for more

details.

MSB

LSB

Following the successful acknowledgment of the slave address, the bus master sends a byte to the TPS6235x,

which contains the address of the register to be accessed. The TPS6235x contains four 8-bit registers accessible

via a bidirectional I2C-bus interface. All internal registers have read and write access.

Table 1. Register Description

Name

Description

VSEL0 (read / write)

VSEL1 (read / write)

CONTROL1 (read / write)

CONTROL2 (read / write)

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Product Folder Link(s): TPS62350, TPS62351 TPS62352, TPS62353 TPS62354, TPS62355, TPS62356

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