TMS320C6713 datasheet(39/148 Pages) TI

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TMS320C6713

FLOATINGPOINT DIGITAL SIGNAL PROCESSOR

SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Table 23. C6713 Device Multiplexed/Shared Pins (Continued)

DESCRIPTION

DEFAULT SETTING

DEFAULT

FUNCTION

MULTIPLEXED PINS

DESCRIPTION

DEFAULT SETTING

DEFAULT

FUNCTION

GDP

PYP

NAME

HINT/GP[1]

135

J20

HD15/GP[15]

174

B14

HD14/GP[14]

173

C14

HD13/GP[13]

172

A15

By default, the HPI peripheral pins are

HD12/GP[12]

168

C15

By default, the HPI peripheral pins are

enabled at reset. McASP1 peripheral

HD11/GP[11]

167

A16

enabled at reset. McASP1 peripheral

pins

and

eleven

GPIO

pins

are

HD10/GP[10]

166

B16

pins

and

eleven

GPIO

pins

are

disabled.

HD9/GP[9]

165

C16

To enable the McASP1 peripheral pins

HD8/GP[8]

160

B17

To enable the McASP1 peripheral pins

and the eleven GPIO pins, an external

HD7/GP[3]

164

A18

and the eleven GPIO pins, an external

pulldown resistor must be provided on

the HD14 pin setting HPI_EN = 0 at

HD4/GP[0]

156

C19

the HD14 pin setting HPI_EN = 0 at

reset.

HD1/AXR1[7]

152

D20

HPI_EN (HD14 pin) = 1

(HPI enabled)

reset.

HD0/AXR1[4]

147

E20

HPI pin function

HPI_EN (HD14 pin) = 1

(HPI enabled)

To use these software-configurable

HCNTL1/AXR1[1]

144

G19

HPI pin function

McASP1 pins and eleven

To use these software-configurable

GPIO pins, the GPxEN bits in the GP

HCNTL0/AXR1[3]

146

G18

McASP1 pins and eleven

GPIO pins are disabled.

GPIO pins, the GPxEN bits in the GP

Enable Register and the GPxDIR bits in

the GP Direction Register must be

HR/W/AXR1[0]

143

G20

GPIO pins are disabled.

Enable Register and the GPxDIR bits in

the GP Direction Register must be

properly configured.

HDS1/AXR1[6]

151

E19

properly configured.

GPxEN = 1:

GP[x] pin enabled

HDS2/AXR1[5]

150

F18

GPxEN = 1:

GP[x] pin enabled

GPxDIR = 0:

GP[x] pin is an input

GPxDIR = 1:

GP[x] pin is an

HCS/AXR1[2]

145

F20

GPxDIR = 0:

GP[x] pin is an input

GPxDIR = 1:

GP[x] pin is an

output

HD6/AHCLKR1

161

C17

output

HD5/AHCLKX1

159

B18

McASP1 pin direction is controlled by

the PDIR[x] bits in the McASP1PDIR

HD3/AMUTE1

154

C20

McASP1 pin direction is controlled by

the PDIR[x] bits in the McASP1PDIR

HD2/AFSX1

155

D18

HHWIL/AFSR1

139

H20

HRDY/ACLKR1

140

H19

HAS/ACLKX1

153

E18

TINP0/AXR0[3]

Timer 0 input

function

McASP0PDIR = 0 (input)

[specifically AXR0[3] bit]

By default, the Timer 0 input pin is

enabled (and a shared input until the

McASP0 peripheral forces an output).

McASP0PDIR = 0 input, = 1 output

TOUT0/AXR0[2]

Timer 0 output

function

TOUT0SEL = 0

(DEVCFG register bit)

[TOUT0 pin enabled and

McASP0 AXR0[2] pin

disabled]

By default, the Timer 0 output pin is

enabled.

To enable the McASP0 AXR0[2] pin, the

TOUT0SEL bit in the DEVCFG register

must be set to 1 (disabling the Timer 0

peripheral output pin function).

The AXR2 bit in the McASP0PDIR

controls

the

direction

(input/output) of the AXR0[2] pin

McASP0PDIR = 0 input, = 1 output

DEVICE CONFIGURATIONS (CONTINUED)

TMS320C6713 Datasheet(PDF) 39 Page - Texas Instruments

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