MTL007
page 4 of 65
PIN DESCRIPTION
ADC Input Interface (RGB or YUV or TMDS Input Data)
Name
Type
Pin No.
Description
IPCLK
I
92
Input pixel clock
VSYNC
I
94
Input Vertical sync
HSYNC/CS
I
93
Input Horizontal or Composite sync
RIN[7:0]/YIN[7:0]
(RIN[5:0])
I
91-84
(89-84)
Red or Y channel or TMDS input data
(Red channel for 6-bit input)
GIN[7:0]/UVIN[7:0]
(GIN[5:0])
I
82-75
(78-75, 91, 90)
Green or UV channel or TMDS input data
(Green channel for 6-bit input)
BIN[7:0]
(BIN[5:0])
I
74-67
(68, 67, 82-79)
Blue or TMDS input data, or Control bit for YUV video input
Bit 4: VPHREF, Video input Horizontal reference signal
Bit 3: VPVS, Video input VSYNC signal
Bit 2: VPODD, Video input ODD/EVEN field signal
Bit 1: VPHS, Video input HSYNC signal
Bit 0: VPCLK, Video input clock signal
(Blue channel for 6-bit input)
RAWHS
I
62
Input source HSYNC for measurement
TDIE
I
66
TMDS digital input enable
CLAMP
O
60
Clamp pulse output for ADC
Display Output Interface
Name
Type
Pin No.
Description
DDCLK1
1
Display output clock
DVSYNC
O
37
Display Vertical sync output
OE
O
39
Display output enable
DHSYNC
O
35
Display Horizontal sync output
DDCLK2
O
38
Display output clock
R1OUT[0:7]
O
33-30, 28, 26-25, 23 Red output even data
, bit[7:2] for 6-rlogin rbit panel
G1OUT[0:7]
O
22, 20-15, 13
Green output even data , bit[7:2] for 6-bit panel
B1OUT[0:7]
O
11-9, 7, 5-3, 2
Blue output even data
, bit[7:2] for 6-bit panel
R2OUT[0:7]
O
128-127, 125-124,
122-119
Red output odd data
, bit[7:2] for 6-bit panel
G2OUT[0:7]
O
118,117, 115, 113-
111, 109,107
Green output odd data , bit[7:2] for 6-bit panel
B2OUT[0:7]
O
106-101, 99-98
Blue output odd data
, bit[7:2] for 6-bit panel
Host Interface
Name
Type
Pin No.
Description
RST#
I
44
System reset input, active low.
SCL
I
48
Serial bus clock
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