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PCA9600DP Datasheet(PDF) 8 Page - NXP Semiconductors

Part # PCA9600DP
Description  Dual bidirectional bus buffer
PDF  32 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9600DP Datasheet(HTML) 8 Page - NXP Semiconductors

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NXP Semiconductors
PCA9600
Dual bidirectional bus buffer
Tamb = -40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V
unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Pins SX and SY
on Standard-mode or Fast-mode
I2C-bus
ISX = ISY = 3 mA; Figure 6
-
0.7
0.74
V
ISX = ISY = 0.3 mA; Figure 5
-
0.6
0.65
V
on 5 V Fm+ I2C-bus
VOL
LOW-level output voltage
ISX = ISY = 7 mA
-
-
1
V
ΔV/ΔT
voltage variation with temperature ISX = ISY = 0.3 mA to 3 mA
-
0
-
%/K
Input logic switching threshold voltages
Pins SX and SY
VIL
LOW-level input voltage
on normal I2C-bus; Figure 7
[3] -
-
425
mV
Vth(IH)
HIGH-level input threshold voltage on normal I2C-bus; Figure 8
580
-
-
mV
ΔV/ΔT
voltage variation with temperature
-
0
-
%/K
Pins RX and RY
VIH
HIGH-level input voltage
fraction of applied VCC
0.55VCC -
-
V
Vth(i)
input threshold voltage
fraction of applied VCC
-
0.48VCC -
V
VIL
LOW-level input voltage
fraction of applied VCC
-
-
0.4VCC
V
Logic level threshold difference
ΔV
voltage difference
SX and SY; SX output LOW
at 0.3 mA to SX input HIGH
maximum
[4] 50
-
-
mV
Thermal resistance
Rth(j-pcb) thermal resistance from junction to
printed-circuit board
SOT96-1 (SO8); average lead
temperature at board interface
-
127
-
K/W
Bus release on VCC failure
VCC
supply voltage
SX, SY, TX and TY; voltage
at which all buses are to be
released at 25 °C
-
-
1
V
ΔV/ΔT
voltage variation with temperature Figure 9
-
-4
-
%/K
Buffer response time[5]
VCC = 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.2 kΩ; no capacitive load
VSX to VTX, VSY to VTY; on
falling input between VSX = input
switching threshold, and VTX
output falling to 50 % VCC
-
50
-
ns
td
delay time
VSX to VTX, VSY to VTY; on
rising input between VSX = input
switching threshold, and VTX
output reaching 50 % VCC
-
60
-
ns
Table 6. Characteristics...continued
PCA9600
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6.1 — 20 December 2021
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