NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

10.1 Calculating system delays and bus clock frequency

PCA9600

PCA9600

SCL

SX

local master bus

VCCM

SCL

MASTER

I2C-BUS

Cs

slave bus

capacitance

Cb

buffered bus

wiring capacitance

Cm

master bus

capacitance

Rm

GND (0 V)

VCCB

buffered expansion bus

TX/RX

TX/RX

SX

Rb

Rs

I2C-BUS

SLAVE

VCCS

remote slave bus

002aac847

Effective delay of SCL at slave: 120 + 17VCCM + (2.5 + 4 × 109 × Cb) × VCCB + 10VCCS (ns).

C = F; V = V.

Figure 15. Falling edge of SCL at master is delayed by the buffers and bus fall times

PCA9600

SX

local master bus

VCCM

SCL

MASTER

I2C-BUS

Cb

buffered bus

wiring capacitance

Cm

master bus

capacitance

Rm

GND (0 V)

VCCB

buffered expansion bus

TX/RX

TX/RX

Rb

002aac848

Effective delay of SCL at master: 115 + (Rm × Cm) + (0.7 × Rb × Cb) (ns).

C = F; R = Ω.

Figure 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times

PCA9600

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© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 6.1 — 20 December 2021

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