7.2.2 Detailed Design Procedure

7.2.2.1 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1μF to

1μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and

improves transient response, noise rejection, and ripple rejection. A higher-value capacitor can be necessary if

large, fast rise-time load transients are anticipated or the device is located several inches from the power source.

The TPS732-Q1 family of devices does not require an output capacitor for stability and has maximum phase

margin with no capacitor. The devices are designed to be stable for all available types and values of capacitors.

In applications where VIN – VOUT < 0.5V and multiple low ESR capacitors are in parallel, ringing can occur when

the product of COUT and total ESR drops below 50nF×Ω. Total ESR includes all parasitic resistances, including

capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR

and trace resistance meets this requirement.

7.2.2.2 Output Noise

A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the

dominant noise source within the TPS732-Q1 family of devices and generates approximately 32μVRMS (10Hz to

100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same

gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:

VN=32μVRMS× R1+R2R2 =32μVRMS×VOUTVREF

(3)

Because the value of VREF is 1.2V, this relationship reduces to:

VNμVRMS =27 μVRMSV ×VOUTV

(4)

where

• CNR does not exist

An internal 27kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage

reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF,

the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of approximately 3.2, giving the

approximate relationship:

VNμVRMS =8.5 μVRMSV ×VOUTV

(5)

where

• CNR = 10nF

This noise reduction effect is shown as RMS Noise Voltage vs CNR in Typical Characteristics.

The TPS73201-Q1 adjustable version does not have the noise-reduction pin available. However, connecting

a feedback capacitor, CFB, from the output to the FB pin reduces output noise and improve load transient

performance.

The TPS732-Q1 family of devices uses an internal charge pump to develop an internal supply voltage sufficient

to drive the gate of the NMOS pass element above VOUT. The charge pump generates approximately 250μV of

switching noise at approximately 2MHz; however, charge-pump noise contribution is negligible at the output of

the regulator for most values of IOUT and COUT.

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TPS732-Q1

SGLS303H – MAY 2005 – REVISED JULY 2025

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