M36W108 datasheet(2/35 Pages) STMICROELECTRONICS

2 / 35 page

M36W108T, M36W108B

2/35

DESCRIPTION

The M36W108 is multi-chip device containing an

8 Mbit boot block Flash memory and a 1 Mbit of

SRAM. The device is offered in the new Chip

Scale Package solutions: LBGA48 1.0 mm ball

pitch and LGA48 1.0 mm land pitch.

The two components, of the package’s overall 9

Mbit of memory, are distinguishable by use of the

three chip enable lines: EF for the Flash memory,

E1S and E2S for the SRAM.

The Flash memory component is identical with the

M29W008 device. It is a non-volatile memory that

may be erased electrically at the block or chip level

and programmed in-system on a Byte-by-Byte ba-

sis using only a single 2.7V to 3.6V VCCF supply.

For Program and Erase operations the necessary

high voltages are generated internally. The device

can also be programmed in standard program-

mers. The array matrix organization allows each

block to be erased and reprogrammed without af-

fecting other blocks.

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature, Programming, Block

Figure 2. LBGA and LGA Connections (Top View)

A11

A14

VSS

DQ3

VCCF

VSS

A18

VCCS

DQ1

DQ2

DQ4

DQ7

DQ5

A19

DQ0

A10

E1S

AI02508

E2S

A13

DQ6

A15

A12

A16

A17

Table 1. Signal Names

A0-A16

Address Inputs

A17-A19

Address Inputs for Flash Chip

DQ0-DQ7

Data Input/Outputs, Command Inputs

for Flash Chip

Chip Enable for Flash Chip

E1S, E2S

Chip Enable for SRAM Chip

Output Enable

Write Enable

Reset for Flash Chip

Ready/Busy Output for Flash Chip

VCCF

Supply Voltage for Flash Chip

VCCS

Supply Voltage for SRAM Chip

VSS

Ground

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