Datasheet_DMR01 June 2003
Registers for DMR01 configuration
The system consists of several registers for programming the desired function. All registers will be reset to 0 with ‘Res’ = ‘0’.
Control register
Register name:
CNT
Access:
R/W
Description:
Control register for programming the function of the DMR-01
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address
Out1
Out0
Br1
Br0
Dec on
Fdet on
Rec on
00H
Description:
Out1,Out0 =
00 : no internal signals available at Pin ‘Datout’ and Pin ‘Clkout’
01 : ‘Aest’ is mapped to ‘Datout’, ‘Clka’ is mapped to ‘Clkout’
10 : ‘Best’ is mapped to ‘Datout’, ‘Clkb’ is mapped to ‘Clkout’
11 : ‘Cest’ is mapped to ‘Datout’, ‘Clkc’ is mapped to ‘Clkout’
Br1,Br0 =
00 : baud rate is set to 1’024 bit/s
01 : baud rate is set to 2’048 bit/s
10 : baud rate is set to 4’096 bit/s
11 : baud rate is set to 8’192 bit/s
Dec on =
0 : Decoder is not enabled
1 : Decoder is enabled
Fdet on =
0 : Frame detector is off
1 : Frame detector is on
Rec on =
0 : Receiver is off (including input amplifier)
1 : Receiver is on
In order to guarantee proper function ‘Rec on’ must be set to ‘0’ before any of Bit2 to Bit5 is changed.
Interrupt register
Register name:
INT
Access:
R/W (write access is only possible for IE)
Description:
Interrupt status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address
IRQ
IE
01H
Description:
IE =
0 : Interrupt capability disabled
1 : Interrupt capability enabled
IRQ =
0 : Interrupt not requested
1 : Interrupt request after received data
An interrupt request will be reset by ‘Res’ = ‘0’ or by reading any of the data registers. In this case the positive edge of
‘CS’ will trigger the clear function. This means that ‘CS’ must be high to start the receiver again.
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