M48T512V datasheet(7/21 Pages) STMICROELECTRONICS

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M48T512Y, M48T512V*

READ Mode

The M48T512Y/V is in the READ Mode whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The unique address specified by the 19 Ad-

dress Inputs defines which one of the 524,288

bytes of data is to be accessed. Valid data will be

available at the Data I/O pins within Address Ac-

cess Time (tAVQV) after the last address input sig-

nal is stable, providing the E and G access times

are also satisfied. If the E and G access times are

not met, valid data will be available after the latter

of the Chip Enable Access Times (tELQV) or Output

Enable Access Time (tGLQV). The state of the eight

three-state Data I/O signals is controlled by E and

G. If the outputs are activated before tAVQV, the

data lines will be driven to an indeterminate state

until tAVQV. If the Address Inputs are changed

while E and G remain active, output data will re-

main valid for Output Data Hold Time (tAXQX) but

will go indeterminate until the next Address Ac-

cess.

Figure 5. READ Mode AC Waveforms

Note: WE = High.

Table 3. READ Mode AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. CL = 5pF.

Symbol

Parameter(1)

M48T512Y

M48T512V

Unit

–70

–85

Min

Max

Min

Max

tAVAV

READ Cycle Time

tAVQV

Address Valid to Output Valid

tELQV

Chip Enable Low to Output Valid

tGLQV

Output Enable Low to Output Valid

tELQX

(2)

Chip Enable Low to Output Transition

tGLQX

(2)

Output Enable Low to Output Transition

tEHQZ

(2)

Chip Enable High to Output Hi-Z

tGHQZ

(2)

Output Enable High to Output Hi-Z

tAXQX

Address Transition to Output Transition

AI02389

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A18

DQ0-DQ7

VALID

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