5.5 Electrical Characteristics

Minimum and Maximum specifications apply from TA of -10°C to 85°C. Typical specifications are at 25°C and VPUP = 3.3V

and 5V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I/O PIN: GENERAL DATA

VPUP

Pull-up Voltage

±5% variation

(3.3V - Standard speed only)

3.13

3.3

3.46

V

4.75

5

5.25

V

RPUP

Pull-up Resistance

(1) (2) (3)

500

Ω

CCABLE

Cable Capacitance

(4) (5)

1.7

nF

CIO

Input Capacitance

(6) (4)

2000

pF

IL

Input Load Current

(7)

7

14

µA

VIL

Input Low Voltage

(8)

0.5

V

VOL

Output Low Voltage

Measured with RPUP = 500Ω,

VPUP = 3.3V

0.4

0.5

V

Measured with RPUP = 500Ω,

VPUP = 5V

0.4

0.5

V

VTL

High-to-Low Switching threshold(4) (3)

(9)

VPUP = 3.3V

0.84

1.72

V

VPUP = 5V

2

3

V

VTH

Low-to-High Switching Threshold(4)

(3) (10)

VPUP = 3.3V

1.64

2.75

V

VPUP = 5V

3.2

4.3

V

VHY

Switching Hysteresis(4) (3) (11)

VPUP = 3.3V

0.44

1.1

V

VPUP = 5V

0.9

1.3

V

(1)

Maximum allowable pull-up resistance is dependent on the number of devices connected and the recovery time. The specified value is

assuming six devices are connected in the system and minimum recovery time.

(2)

Resistance tolerance to be within 1% or less.

(3)

VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, single-wire timing, and capacitive

loading on SDQ single-wire serial interface pin. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower

values of VTL, VTH, and VHY.

(4)

Specified by design, characterization or simulation only. Not production tested.

(5)

System requirement.

(6)

Maximum Capacitance value represents the internal parasitic capacitance when VPUP is first applied. Once the parasitic charge

storage capacitance is charged, normal logic transitions are not affected.

(7)

Applicable when SDQ single-wire serial interface is HIGH (at VPUP) and the device is in idle mode (no digital activity or memory

access). The numbers indicates the stand-by current consumption.

(8)

The voltage on SDQ single-wire serial interface needs to be less or equal to VILMAX at all times the host is driving SDQ single-wire

serial interface to a logic 0 level.

(9)

Voltage below which, during a falling edge on SDQ single-wire serial interface, logic 0 is detected.

(10) Voltage above which, during a rising edge on SDQ single-wire serial interface, logic 1 is detected.

(11) After VTH is crossed during a rising edge on SDQ single-wire serial interface pin, the voltage on SDQ single-wire serial interface must

drop by at least VHY to be detected as logic 0.

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TMF0020

SLVSJQ4 – MAY 2026

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