Table 6-1. FRAM Data Memory Map (continued)

ADDRESS RANGE

TYPE (1)

DESCRIPTION

PROTECTION CODES (NOTES)

0900h to 09FFh

R/(W)

Data Memory Pages 72 to 79 (Block 9)

(Protection controlled by address 1FA9h)

(1)

R = Read, W = Write

In FRAM devices, digital information is stored as polarization in a dielectric. This polarization can be lost at a

temperature-dependent rate. Increasing temperatures increase the de-polarization rate. Data Retention metrics

are listed in the Section 5.6 table.

6.3.2 FRAM Status Memory

As shown in Table 6-1, the data memory of the TMF0020 consists of 10 contiguous blocks of FRAM memory.

Blocks 0 to 9 are 256 bytes each, and each block is formed by eight adjacent memory pages.

In addition to the data memory, the TMF0020 consists of the status memory starting at address 1FA0h as shown

in Table 6-2. The register page in the status memory consists of 10 protection control bytes and one byte each to

lock the memory block and the register page.

Both the 10 protection control bytes and the memory block lock byte control the access to the 10 data

memory blocks. By default, the memory blocks are set to open access. A protection byte value of 55h sets

the corresponding memory block to write protection mode, whereas a protection byte value of AAh sets the

corresponding memory block to EPROM mode.

If the memory block lock byte is programmed to either 55h or AAh, copy protection is set for all write-protected

data memory blocks (memory blocks in EPROM mode are not affected). Similarly, if the register page lock byte

is programmed to either 55h or AAh, copy protection is set for the entire register page.

Setting a memory location into write protection mode allows the copy-scratch pad operation, but prevents data

from being changed. This allows memory to be reprogrammed with the same data, refreshing the polarization for

data retention longevity.

As compared to write protection, copy protection blocks the copy-scratchpad function. Only use the copy-protect

feature after setting all write-protected blocks and associated protection control bytes to the final values. Note

that copy protection does not prevent copying data across devices. When set to 55h or AAh, the protection

control registers and the lock bytes self-write-protect. Any other setting allows unrestricted write access.

Addresses 1FC3h and 1FC4h are available for programming an optional manufacturer ID. These values are

read by the host, for example, to associate an end-user product with a TMF0020. At address 1FC2h, the

TMF0020 stores a byte for locking the manufacturer ID, with a default value of 00h. After writing AAh or 55h to

this location, the manufacturer ID and lock byte are permanently write protected.

Table 6-2. FRAM Status Memory Map

ADDRESS RANGE

TYPE (1)

DESCRIPTION

PROTECTION CODES (NOTES)

1FA0h

R/W

Protection Control Byte (Block 0)

55h: Write Protect Block 0

AAh: EPROM Mode Block 0

55h or AAh: Write Protect 1FA0h

1FA1h

R/W

Protection Control Byte (Block 1)

55h: Write Protect Block 1

AAh: EPROM Mode Block 1

55h or AAh: Write Protect 1FA1h

1FA2h

R/W

Protection Control Byte (Block 2)

55h: Write Protect Block 2

AAh: EPROM Mode Block 2

55h or AAh: Write Protect 1FA2h

1FA3h

R/W

Protection Control Byte (Block 3)

55h: Write Protect Block 3

AAh: EPROM Mode Block 3

55h or AAh: Write Protect 1FA3h

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TMF0020

SLVSJQ4 – MAY 2026

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