APPLICATION INFORMATION

Loop Compensation and External Parts Selection

Ref

R1

R2

Voltage Devider

Switching Modulator

PWM

Logic

control

Driver

DRVH

DRVL

Vin

Lx

ESR

Co

Vc

1

2

3

SW

O

O

f

f

ESR C

p

=

£

´

´

(3)

[

]

10

OUT

RIPPLE

FBx

V

V

mV

V

=

´

(4)

TPS53124

A buck converter system using D-CAP™ Mode can be simplified as below.

Figure 12. Simplifying the Modulator

The output voltage is compared with internal reference voltage after divider resistors,R1 and R2. The PWM

comparator determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough

to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The dc

output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage

increase.

Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external components

configuration and extremely short response time, a sufficient amount of feedback signal needs to be provided by

external circuit to reduce jitter level. This is due to not employing an error amplifier in the loop. The required

signal level is approximately 10 mV at the comparing point(VFB terminal). This gives Vripples at the output node

becomes Equation 4. The output capacitor’s ESR should meet this requirement.

14

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