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5L35021 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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5L35021 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 40 page  1 ©2017-2025 Renesas Electronics Corporation December 15, 2025 Description The 5L35021 is a member of the VersaClock 3S programmable clock generator family with 1.8V operation voltage, and is designed for industrial, consumer, and PCI Express applications. The device features a 3 PLL architecture design; each PLL is individually programmable and allowing up to 6 unique frequency outputs. The 5L35021 has built-in features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshoot Reduction Technology (ORT) and extreme low power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5L35021 again through the I2C interface. The device has programmable VCO and PLL source selection, allowing power-performance optimization based on the application requirements. Typical Applications ▪ Embedded computing devices ▪ Consumer application crystal replacements ▪ SmartDevice, Handheld, and Consumer applications Key Specifications ▪ PCIe Gen1/2/3 compliant ▪ Typical 1.5ps rms jitter integer range: 12kHz–20MHz ▪ Typical ultra-power-down current 50μA ▪ < 2μA RTC clock in Suspend Mode operation Features ▪ Configurable OE pin function as OE, PD#, PPS or DFC control function ▪ Configurable PLL bandwidth; minimizes jitter peaking ▪ PPS: Proactive Power Saving features save power during the end device power down mode ▪ PPB: Performance Power Balancing feature allows minimum power consumption based on required performance ▪ DFC: Dynamic Frequency Control feature allows user to dynamically switch between and up to 4 different frequencies smoothly ▪ Spread spectrum clock to lower system EMI ▪ I2C interface ▪ Suspend Mode, featuring RTC clock only when system goes into low-power operation modes Output Features ▪ 2 DIFF outputs with configurable LPHSCL, LVCMOS output pairs: 1MHz–250MHz (125MHz with LVCMOS mode) ▪ 1 LVCMOS output: 1MHz–125MHz ▪ LVPECL, LVDS, CML and SSTL logic can be easily supported with the LP-HCSL outputs. See application note AN-891 for alternate terminations ▪ Maximum of 5 LVCMOS outputs as REF + 3 × SE + 2 × DIFF_T/C as LVCMOS ▪ Low-power 32.768kHz clock supported for SE1 output Block Diagram OSC PLL2 DIFF1 PLL3 SDA_DFC0 SEL_DFC/ SCL_DFC1 VDDDIFF 1 CLKIN/X1 32.768K DCO Calibration PLL1 Mux & Divider X2 VDD18 Programmable Load Capacitor DIFF1B DIFF2 DIFF2B VDDDIFF 2 VDDSE1 SE1 OE1 VDDA VBAT 5L35021 Datasheet VersaClock® 3S Programmable Clock Generator |
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